A packaged integrated circuit (IC) chip that provides input/output (I/O) signal fail safe verification is disclosed. The packaged IC chip includes a first processing unit, a first control peripheral coupled to receive a first processed signal from the processing unit and to provide an output signal, and compare logic. The compare logic is coupled to receive the output signal and a comparison signal, to compare the output signal and the comparison signal, and to provide an error signal responsive to a difference between the output signal and the comparison signal.

A method tests at least three devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices, and shifting test data in the test chains of each of the devices and storing a result of the comparison in a first position of the test chains of each of the devices. The comparing and the shifting and storing are repeated until all the stored test data has been compared. The at least three devices may have a same functionality and a same structure.

A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

A measurement system of a device under test (DUT) includes a reference clock synthesizer configured to generate a master reference clock signal, a transmitter unit connected to the reference clock synthesizer and configured to connect to the DUT, and a measurement control system connected to the transmitter unit and configured to control the transmitter unit to generate a test signal pattern based on a first reference clock signal derived from the master reference clock signal, and generate a signal for passing through the DUT based on the test signal pattern. A receiver unit connected to the reference clock synthesizer is configured to connect to the DUT and to detect the signal and generate a digital signal based on the signal and a second reference clock signal derived from the master reference clock signal. The measurement control system is configured to provide an output signal based on the digital signal.

A packaged integrated circuit (IC) chip that provides input/output (I/O) signal fail safe verification is disclosed. The packaged IC chip includes a first processing unit, a first control peripheral coupled to receive a first processed signal from the processing unit and to provide an output signal, and compare logic. The compare logic is coupled to receive the output signal and a comparison signal, to compare the output signal and the comparison signal, and to provide an error signal responsive to a difference between the output signal and the comparison signal.

A spectral leakage-driven loopback method for predicting performance of a mixed-signal circuit. The method includes generating, by an on-chip Digital Signal Processor (DSP) core, a digitally-synthesized single-tone sinusoidal stimulus. A nonlinear digital-to-analog-converter (DAC) channel is sampled. A DAC output signal is supplied to a nonlinear analog-to-digital converter (ADC) channel through an analog loopback path. Each of the DAC channel and the ADC channel are measured for a production testing. The on-chip DSP core performs postprocessing and predicting harmonics of the two individual DAC and ADC channels.

A test assembly for testing an antenna-in-package (AiP) device includes a socket over a circuit board, where the socket includes an opening for receiving the AiP device; a plunger configured to move along sidewalls of the opening, where during testing of the AiP device, the plunger is configured to cause the AiP device to be pressed towards the circuit board such that the AiP device is operatively coupled to the circuit board via input/output connections of the AiP device and of the circuit board; and a loadboard disposed within the socket and between the plunger and the AiP device, where the loadboard includes a coupling structure configured to be electromagnetically coupled to a transmit antenna and to a receive antenna of the AiP device, so that testing signals transmitted by the transmit antenna are conveyed to the receive antenna externally relative to the AiP device through the coupling structure.

A semiconductor memory device includes first bumps positioned along a first direction; second bumps positioned in parallel to the first bumps along the first direction; first registers connected with the first bumps; and second registers connected with the second bumps. The first registers and the second registers are sequentially connected and form a shift register.

Methods, systems, and devices for testing a die using a segmented digital die ring are described. A segmented digital die ring may include multiple signal line segments, each coupled with a test segment circuit, and a control circuit. A test segment circuit may generate a digital feedback signal that indicates a condition of a respective signal line segment. The control circuit may generate a single output signal, indicative of the condition of the signal line segments. By utilizing digital testing circuitry and a single digital output signal, a layout area of the segmented digital die ring be minimized and a power consumption associated with the testing operation may be reduced.

Various approaches to implementing digital loopback in a radio frequency (RF) system are disclosed. An example RF system includes a receiver that includes an ADC and a transmitter that includes a DAC. The apparatus includes multiple digital loopback circuits provided at different points between the digital domain processing of the receiver and the transmitter. Each digital loopback circuit may include a combiner and one or more weighing circuits, which make the circuit programmable. The combiner of a given digital loopback circuit is configured to combine a RX signal and a TX signal at a particular point of the digital domain processing of the receiver and the transmitter where said digital loopback circuit is implemented. The one or more weighting circuits are configured to define the how much of the TX signal and/or RX signal is used for said combination.