The invention concerns a circuit for transferring a data from one clock domain to another clock domain, the circuit comprising: a digital circuit configured to generate a data signal synchronized with a source clock signal, and to receive such data by sampling the data signal synchronized with a target clock signal; a phase comparator which is configured to determine a phase relationship between the source clock signal and the target clock signal; and a data signal synchronization circuit configured to receive data signal transitions that are synchronized with the source clock signal, and to provide a synchronized data signal transitions of which are synchronized with the target clock signal.

An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

An automated testing machine with data processing function and an information processing method thereof are introduced. The automated testing machine includes a test head for testing more than one device under testing (DUT), and the test head further includes a test processing unit for providing more than one electrical test signal to the DUTs and conducting a processing and analyzing on more than one electrical feedback data fed back from the DUTs, so as to generate analysis result information. With the test processing unit capable of conducting data processing directly provided in the test head, signals obtained from the DUTs can be directly analyzed and processed to enable increased data processing efficiency, increased convenience in use and reduced costs of the automated test machine and the information processing method thereof.

A linearity test system for a chip, a linearity signal providing device, and a linearity test method for the chip are provided. The linearity test method for the chip includes steps as follows: providing a reference clock signal and a receiver input signal to a chip under test, wherein the reference clock signal and the receiver input signal have a phase difference in time domain; and determining a linearity of a phase interpolator of the chip under test based on a plurality of phase signals of the chip under test corresponding to the reference clock signal and the receiver input signal.

An integrated circuit includes a multiplexer circuit coupled to receive a first clock signal and a second clock signal and coupled to provide an output clock signal to a channel. A protection circuit is coupled to receive a feedback signal from the channel. The protection circuit causes the multiplexer circuit to provide oscillations in the second clock signal to the output clock signal in response to the feedback signal indicating that the channel is idle to cause the channel to be in a protection mode that reduces degradation from bias temperature instability. The protection circuit causes the multiplexer circuit to provide oscillations in the first clock signal to the output clock signal in response to the feedback signal indicating that the channel is active.

A test and measurement system includes a primary instrument having an input for receiving a test signal for measurement or analysis from a Device Under Test (DUT) and generating a test waveform from the test signal, and a duplicator for sending a copy of the test waveform to one or more secondary instruments. The one or more secondary instruments are each structured to access the copy of the test signal for analysis, and each of the one or more secondary instruments includes a receiver structured to receive a command related to measurement or analysis of the copy of the test waveform, one or more processes for executing the received command, and an output for sending results of the executed command to be displayed on a user interface that is separate from any user interface of the one or more secondary instruments.

A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

A data transmission apparatus includes lanes, a first clock generation circuit, a second clock generation circuit, a first circuit, and a second circuit. The first clock generation circuit can generate a first clock as a reference for data transmission in a first lane. The second clock generation circuit can generate a second clock as a reference for data transmission in a second lane. The first circuit can determine a shift amount by notification of a first delay amount of the first lane and a second delay amount of the second lane to cause a delay amount of one of the first clock and the second clock to match a delay amount of the other of the first clock and the second clock. The second circuit can shift the first delay amount or the second delay amount based on the determined shift amount.

An automated testing machine with data processing function and an information processing method thereof are introduced. The automated testing machine includes a test head for testing more than one device under testing (DUT), and the test head further includes a test processing unit for providing more than one electrical test signal to the DUTs and conducting a processing and analyzing on more than one electrical feedback data fed back from the DUTs, so as to generate analysis result information. With the test processing unit capable of conducting data processing directly provided in the test head, signals obtained from the DUTs can be directly analyzed and processed to enable increased data processing efficiency, increased convenience in use and reduced costs of the automated test machine and the information processing method thereof.