In order to increase test coverage of integrated circuits with multiple clock domains, during a capture portion of a scan test, the functional clock signals, associated with a respective one of the clock domains are synchronized to ensure back and forth capture between the faster and slower clock domain. Each of the plurality of clock signals is generated such that an active edge of each faster clock signal occurs one clock period of the faster clock signal before an active edge of each slower clock signal.

Disclosed is a fan-out buffer which includes a first channel that includes a first delay circuit adjusting a first delay time of a calibration test signal depending on a first delay control signal, a second channel that includes a second delay circuit adjusting a second delay time of the calibration test signal depending on a second delay control signal, a first edge-to-pulse converter that detects a first edge included in a first time domain reflectometry (TDR) waveform of an output terminal of the first channel and generates a first start pulse signal including a first pulse, a second edge-to-pulse converter that generates a second start pulse signal including a second pulse, a stop pulse signal generator that generates a stop pulse signal including a first stop pulse, and a first delay control signal generator that calculates a phase difference generates the first delay control signal.

A processing system includes: main and shadow processing cores configured to operate in lockstep based on a core clock. The main processing core includes a main processing core and a main debug circuit. The shadow processing core includes a shadow functional core and a shadow debug circuit. A redundancy checker circuit is configured to assert an alarm signal when a discrepancy between outputs from the main and shadow functional cores is detected. A debug bus synchronizer circuit is configured to receive input debug data in synchrony with a debug clock, and provide synchronized debug data in synchrony with the core clock to a debug bus based on the input debug data, where the main and shadow debug circuits are configured to receive the synchronized debug data in synchrony with the core clock from the debug bus, and where the debug clock is asynchronous with respect to the core clock.

One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

In one embodiment, a system comprises: a global clock input for receiving a global clock, a plurality of partitions; and a skew tolerant interface configured to compensate for clock skew differences between a global clock from outside at least one of the partitions and a balanced local clock within at least one of the partitions. The partitions can be test partitions. The skew tolerant interface can cross a mesochronous boundary. In one exemplary implementation, the skew tolerant interface includes a deskew ring buffer on communication path of the at least one partition. pointers associated with the ring buffer can be free-running and depend only on clocks being pulsed when out of reset. The scheme can be fully synchronous and deterministic. The scheme can be modeled for the ATPG tools using simple pipeline flops. The depth of the pipeline can be dependent on the pointer difference for the read/write interface. The global clock input can be part of a scan link.

A method for marking relevant data within an acquired set of data in accordance with an embodiment includes receiving a location of a first synchronization event within a synchronizing time pulse synchronized with the acquired set of data, searching the synchronizing time pulse within a predetermined window for the first synchronization event based on the location, identifying the first synchronization event based on the search, and obtaining data from the acquired set of data within an offset range determined based on the identified first synchronization event. The steps are then iteratively repeated for a number of periods.

An electric meter that is configured to regenerate meter state data after a power loss includes a memory with at least one volatile and non-volatile memory device and a processor connected to the memory. The processor is configured to retrieve a backup copy of meter state data and a plurality of meter input data samples that were generated after the backup copy of the meter state data and prior to the power loss from a non-volatile memory device. The processor is configured to regenerate meter state data by updating the backup copy of meter state data with the plurality of meter input data samples to regenerate the meter state data at the time of a final meter input data sample prior to the power loss.

A clock jitter measurement circuit includes: an internal signal generator configured to generate a single pulse signal and an internal clock signal which are both synchronized with an input clock signal received by the clock jitter measurement circuit, a plurality of edge delay cells serially connected to each other and configured to generate a plurality of edge detection signals respectively corresponding to a plurality of delay edges obtained by delaying an edge of the internal clock signal, a plurality of latch circuits configured to latch the single pulse signal in synchronization with the plurality of edge detection signals and output a plurality of sample signals, and a count sub-circuit configured to count a number of activated sample signals of the plurality of sample signals and output a count value based on the counted number of activated sample signals.

A first circuitry may be configured to generate a first output based on an input and send an indication responsive to detection of an error while the first output is generated. A second circuitry may be configured to generate a second output based on the input. A wrapper circuitry may be configured to compare the first output and the second output to check correctness by default, and responsive to receipt of the indication, select the second output as a system output without checking for correctness by comparing the first output and the second output. In some implementations, the second circuitry may be configured to send a second indication responsive to detection of a second error while the second output is generated. The wrapper circuitry may be configured to, responsive to receipt of the second indication, ignore the check for correctness.

A semiconductor device includes a memory cell array, a plurality of word lines, a plurality of bit line pairs, a column selection circuit coupling a bit line pair in a selected column in the plurality of bit line pairs to first and second output signal lines on the basis of a column selection signal, and a sense amplifier amplifying the voltage difference between the first and second output signal lines. The semiconductor device further includes: a scan flip flop to which the data can be input via a scan chain; and a voltage setting circuit setting the first and second output signal lines to voltage according to the data held in the scan flip flop in a scan test.