The present disclosure describes exemplary methods and systems that are applicable for hardware authentication, counterfeit detection, and in-field tamper detection in both printed circuit board and/or integrated circuit levels by utilizing random variations in boundary-scan path delay and/or current in the industry-standard JTAG-based design-for-test structure to generate unique device identifiers.

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

An implementation of a system disclosed herein includes a decompressor logic with the capability to vary a level of decompression of a scanning input signal based on value of compression program bits and a compressor logic to generate a scanning output signal, the compressor logic including a plurality of XOR logics, wherein the output of the plurality of XOR logics is selected based on the compression program bits.

A method and an apparatus for testing a chip, as well as a storage medium, and a chip thereof are provided. The chip includes an operation module. The method includes receiving, via a first pin of the chip, a test control signal indicating a test type of the operation module; performing a first test for the operation module using a first test vector based on the test type; or performing a second test for the operation module using a second test vector, where the first test is a test for the memory included in the operation module and the second test is a test for the functional logic in included in the operation module.

A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains.

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

The present application provides a parameter setting method and apparatus, a system, and a storage medium. The parameter setting method includes: obtaining first setting values of multiple memory parameters and storage locations of the multiple memory parameters in a non-volatile memory; generating a first parameter setting instruction according to the first setting value and the storage location of each memory parameter; and sending the first parameter setting instruction to a test device, so that the test device sets the memory parameter stored at the storage location in the non-volatile memory as the first setting value.

Method and apparatus to test an integrated circuit includes retrieving power distribution data relating to an integrated circuit and designating a segment that includes at least one component of the integrated circuit. A switching limit associated with the segment may be set based on the power distribution data. Processes further generate a testing pattern that includes the determined switching limit associated with the segment.

A test interface board includes a first input terminal, a second input terminal, an output terminal, and a transmission line. The first input terminal receives a first test signal for testing a semiconductor device. The second input terminal receives a second test signal for testing the semiconductor device. The output terminal outputs the first test signal and the second test signal to the semiconductor device. The transmission line electrically connects the first input terminal, the second input terminal, and the output terminal such that the first test signal and the second test signal are merged.

An implementation of a system disclosed herein includes a decompressor logic with the capability to vary a level of decompression of a scanning input signal based on value of compression program bits and a compressor logic to generate a scanning output signal, the compressor logic including a plurality of XOR logics, wherein the output of the plurality of XOR logics is selected based on the compression program bits.