Neutron soft error rate derivation is calculated from data at the low energy neutron radiation. An outline value of an SEU cross-section function corresponding to a given neutron energy value is outputted. This outline value and the low energy neutron spectrum data are used to calculate an error count basic value of errors to occur over time. An error count actual measurement value over time is calculated from an error count during radiation of low energy neutrons and low energy neutron radiation time. The error count basic value and the error count actual measurement are used to calculate a proportionality coefficient of the SEU cross-section function. While holding a natural neutron spectrum, an error rate calculator outputs a neutron flux corresponding to a neutron energy value. The neutron soft error rate is calculated by an integration operation of multiplying the SEU cross-section function with the natural neuron spectrum.

Method and system for Single Event Latchup (SEL) current surge mitigation involves monitoring data signals for a protected device and deriving from them a detected signature comprised of one or more detected signature vector components. The detected signature vector components are compared to previously stored signature vector components. Based on the comparing, the system selectively differentiates between the occurrence of standard power surges associated with normal operation of the protected device, and a non-standard current surge which requires cycling power of the protected device for continued proper functioning of the protected device.

An integrated circuit comprising a detection circuit portion for detecting an electromagnetic pulse attack on the integrated circuit is provided. The detection circuit portion comprises a shadow flip-flop comprising a clock input and a clock net connected to said clock input. The detection circuit portion also comprises a clock gate connected to the clock net that is controlled by an enable signal to selectively be in an open state in which the clock gate passes a clock signal to the clock net or in a closed state in which the clock gate does not pass the clock signal to the clock net. The detection circuit portion further comprises an error circuit portion, wherein the error circuit portion is arranged to selectively output an error signal if: the shadow flip-flop is clocked by a signal from the clock net and the clock gate is in the closed state.

According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.

A system and method to manage a single event latched (SEL) condition, the method including operations to monitor, for a predetermined condition associated with single event latched (SEL) states, a reset signal output from a watchdog device to a microprocessor, wherein the reset signal is responsive to a malfunction condition associated with the microprocessor. The method further includes operations to control provision of power to the microprocessor in response to detection of the predetermined condition.

Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.

According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.

Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.

A semiconductor device includes a substrate, first electronic circuitry formed on the substrate, a first diode buried in the substrate under the first electronic circuitry, and a first fault detection circuit coupled to the first diode to detect energetic particle strikes on the first electronic circuitry.

A semiconductor test device includes an actuator holding a radiation source and adjusting a distance between the radiation source and a sample, and a controller controlling an operation of the actuator and calculating a soft error rate (SER) of the sample based on the distance between the radiation source and the sample. The controller calculates a first distance between the radiation source and the sample at which the SER of the sample becomes zero, and calculates a metal-to-dielectric ratio of the sample based on the first distance.