An integrated circuit detection method, apparatus, and system are disclosed, which relate to the field of electronics and resolve a problem of detecting an electrical parameter of an integrated circuit on a printed circuit board in a power-on state. A specific solution is as follows: N detection circuits (101) are disposed, where each detection circuit (101) is connected to a different integrated circuit (102), the detection circuit (101) is provided with a first detection point (a) and a second detection point (b), and the detection circuit (101) is configured to detect the electrical parameter of the integrated circuit (102) that is connected to the detection circuit (101); and N is an integer greater than or equal to 1. The solution is used in a process of detecting the electrical parameter of the integrated circuit on the printed circuit board.

An integrated circuit detection method, apparatus, and system are disclosed, which relate to the field of electronics and resolve a problem of detecting an electrical parameter of an integrated circuit on a printed circuit board in a power-on state. A specific solution is as follows: N detection circuits (101) are disposed, where each detection circuit (101) is connected to a different integrated circuit (102), the detection circuit (101) is provided with a first detection point (a) and a second detection point (b), and the detection circuit (101) is configured to detect the electrical parameter of the integrated circuit (102) that is connected to the detection circuit (101); and N is an integer greater than or equal to 1. The solution is used in a process of detecting the electrical parameter of the integrated circuit on the printed circuit board.

A semiconductor device is provided with: a first circuit; a plurality of pattern generators connected to the first circuit and each supplying a test pattern to the first circuit; a pattern-generator control circuit controlling each of the plurality of pattern generators; a pattern compressor compressing a result output from the first circuit in response to supply of the test patterns from the plurality of pattern generators; a pattern-compressor control circuit controlling the pattern compressor; and a self-diagnosis control circuit connected to the pattern-generator control circuit and the pattern-compressor control circuit, and controlling the pattern-generator control circuit such that stop timings of the test patterns differ from one another among the plurality of pattern generators.

Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between a transmitting device and a receiving device operating at high speed with low power utilization. Communication is performed using group signaling over sets of four wires using a vector signaling code, where each wire of a set carries a low-swing signal that may take on one of four signal values. Topologies and designs of wire sets are disclosed with preferred characteristics for group signaling communications.

Disclosed is a semiconductor integrated circuit including a logic circuit, and a plurality of scan flip-flop circuits that hold input data or output data of the logic circuit and are capable of forming a scan chain for executing a scan test of the logic circuit. Each scan flip-flop circuit includes a scan data input part that receives input of scan data for the scan test, a normal data input part that receives input of normal data different from the scan data, and a data holding part capable of separately holding the normal data and the scan data.

A method, system and computer program product, the method comprising: obtaining circuit information, comprising description of groups of pins of electronic chips; obtaining a description of a test comprising a plurality of rules specifying: an identifier, a first group of pins, a second group of pins, a first action to take upon successful interconnection of the first and second groups, and a second action to take upon failure, wherein the first action and second actions are one of: finish with success, finish with failure, and a rule ID of a subsequent rule to check; checking the plurality of rules, comprising checking a sequence of rules starting with a first rule, and wherein each subsequent rule is selected as the first or second action of a preceding rule, in accordance with whether the preceding rule succeeded or failed, respectively; and outputting a result of the plurality of rules.

Integrated circuits (12) are manufactured by printing an array of circuit elements CE each containing an integrated circuit and associated testing circuitry (14). A plurality of integrated circuits within the array are tested in parallel to generate a corresponding plurality of individual test result signals. These individual test result signals are combined to form a combined test result signal indicating whether any of the plurality of integrated circuits tested in parallel operated incorrectly during their testing. If the combined test result signal indicates any faulty integrated circuits, then the entire plurality of integrated circuits (e.g. an entire row or column) may be discarded. The array of tested integrated circuits are then separated into discrete integrated circuits and are also separated from their testing circuit. Contacts (16, 18, 20) providing power signals, clock signals, and the reading of the combined test result signals are located at the periphery of a substrate sheet onto which the array of circuit elements are printed.

Integrated circuits (12) are manufactured by printing an array of circuit elements CE each containing an integrated circuit and associated testing circuitry (14). A plurality of integrated circuits within the array are tested in parallel to generate a corresponding plurality of individual test result signals. These individual test result signals are combined to form a combined test result signal indicating whether any of the plurality of integrated circuits tested in parallel operated incorrectly during their testing. If the combined test result signal indicates any faulty integrated circuits, then the entire plurality of integrated circuits (e.g. an entire row or column) may be discarded. The array of tested integrated circuits are then separated into discrete integrated circuits and are also separated from their testing circuit. Contacts (16, 18, 20) providing power signals, clock signals, and the reading of the combined test result signals are located at the periphery of a substrate sheet onto which the array of circuit elements are printed.

A graphical tool generates test scenarios to be simulated on an integrated circuit. The tool provides for the assembly of a graphical flow chart that represents source code associated with test scenarios, which helps alleviate the need for manual coding and de-bugging.

A semiconductor device includes a scan input circuit, a master latch, a slave latch, a first inverter, and a scan output circuit. The scan input circuit is configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal. The master latch is configured to latch the first select signal and output a first output signal. The slave latch is configured to latch the first output signal and output a second output signal. The first inverter is configured to invert the second output signal. The scan output circuit is configured to receive a signal output from the slave latch and an external signal and output a first scan output signal.