Provided test method and apparatus of communication chip, device and medium. The test method of communication chip includes receiving end test method and transmitting end test method. The receiving end test method of the communication chip includes: an idle time slot of the receiving end of the communication chip is detected in a running process of the communication chip; a test vector is generated, and a standard result corresponding to the test vector is generated; a data frame containing the test vector is constructed, and the data frame is sent to the receiving end of the communication chip in the idle time slot to enable the receiving end of the communication chip to process the data frame; and a chip processing result uploaded by the receiving end of the communication chip is received, and the standard result is compared with the chip processing result.

A test and measurement system includes a machine learning system configured to communicate with a test automation system, a user interface configured to allow a user to provide one or more user inputs and to provide results to the user, and one or more processors, the one or more processors configured to execute code that causes the one or more processors to receive one or more user inputs through the user interface, the one or more user inputs at least identifying a selected machine learning system configuration to be used to configure the machine learning system, receive a waveform created by operation of a device under test, apply the configured machine learning system to analyze the waveform, and provide an output of predicted metadata about the waveform.

An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes a first processor configured to execute a custom BMC firmware stack, and a second processor including executable instructions for receiving a request to perform a test on the first processor in which the request is received through a secure communication session established with a remote IHS. The instructions further perform the acts of controlling the first processor to perform the test according to the request, the first processor generating test results associated with the test, and transmitting the test results to the remote IHS through the secure communication session.

An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes a first processor configured to execute a custom BMC firmware stack, and a second processor including executable instructions for receiving a request to perform a test on the first processor in which the request is received through a secure communication session established with a remote IHS. The instructions further perform the acts of controlling the first processor to perform the test according to the request, the first processor generating test results associated with the test, and transmitting the test results to the remote IHS through the secure communication session.

System analysis by receiving a model of a complex system design. The model includes at least one layer. The analysis includes performing a plurality of simulations of the performance of the layer. The number of simulations is determined according to a number of system components associated with the layer. The analysis further includes determining a worst-case result for a set of simulations from the plurality of simulations and assigning the worst-case result to an overall system simulation.

A system and method for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.

A semiconductor integrated circuit includes scan chains, each of which includes a serial connection of sequential circuits and performs a shift register operation in a scan test; and an integrated clock gating (ICG) chain composed by coupling, to one another, ICG circuits, each of which individually supplies a corresponding one of the scan chains with a circuit clock signal to operate the sequential circuits. In the ICG chain, an ICG enable propagation signal for controlling timing when the ICG circuits output the circuit clock signals propagates through a signal line and is input sequentially to the ICG circuits. The ICG circuits output the circuit clock signals at respective timings that are different among the scan chains.

Embodiments relate to a system, program product, and method for integrating compiler-based testing in post-silicon validation. The method includes generating a test program through a device-under-test (DUT). The method also includes generating a plurality of memory intervals and injecting the plurality of memory intervals into the test program. The method further includes injecting a plurality of compiled test snippets into the test program and executing one or more post-silicon validation tests for the DUT with the test program.

A method for recovering data included in a digitally modulated signal is described. The digitally modulated signal includes a symbol sequence. The method includes providing a mathematical model of the digitally modulated signal, the mathematical model describing the digitally modulated signal in terms of the symbol sequence and describing the digitally modulated signal in terms of a step response and/or an impulse response, and wherein the mathematical model also takes disturbances into account; and processing the digitally modulated signal based on the mathematical model, thereby recovering the data included in the digitally modulated signal. The disturbances include a random disturbance component modelled as a Gaussian disturbance, and include an inter-symbol interference component modelled as Gaussian noise, and wherein a dependence of the at least one step response on the symbol sequence is neglected within the mathematical model. Further, a measurement instrument and a measurement system are described.

A test and measurement system includes a test and measurement device configured to receive a signal from a device under test, and one or more processors configured to execute code that causes the one or more processors to generate a waveform from the signal, apply an equalizer to the waveform, receive an input identifying one or more measurements to be made on the waveform, select a number of unit intervals (UIs) for a known data pattern, scan the waveform for the known data patterns having a length of the number of UIs, identify the known data patterns as short pattern waveforms, apply a machine learning system to the short pattern waveforms to obtain a value for the one or more measurements, and provide the values of the one or more measurements for the waveform. A method includes receiving a signal from a device under test, generating a waveform from the signal, applying an equalizer to the waveform, receiving an input identifying one or more measurements to be made on the waveform, selecting a number of unit intervals (UIs), scanning the waveform to identify short pattern waveforms having a length equal to the number of UIs, applying a machine learning system to the short pattern waveforms to obtain a value for the one or more measurements, and providing the values of the one or more measurements for the waveform from the machine learning system.