A system, method, and computer program are provided for combining results of event processing received from a plurality of virtual processes or servers. In use, an event is sent to a plurality of virtual processes or virtual servers. Further, a result of processing of the event is received from each of the virtual processes or virtual servers. In addition, the results received from the plurality of virtual processes or virtual servers are combined.

A method for testing circuit elements at one or more manufacturing stages comprising receiving, at a circuit verifier a fingerprint of at least a circuit element to be manufactured, wherein the fingerprint further comprises at least an expected output corresponding to at least a test input, transmitting, from the circuit verifier the at least a test input to the at least a circuit element, receiving, at the circuit verifier at least a test output from the at least a circuit element, and comparing, by the circuit verifier the at least a test output to the at least an expected output of the fingerprint of the at least a circuit element.

Example embodiments are disclosed of systems and methods for predicting failure probabilities of future product tests of a testing sequence based on outcomes of prior tests. Predictions are made by a machine-learning-based model (MLM) trained with a set of test-result sequence records (TRSRs) including test values and pass/fail indicators (PRIs) of completed tests. Within training epochs over the set, iterations are carried out over each TRSR. Each iteration involves sub-iterations carried out successively over test results of the TRSR. Each sub-iteration involves (i) inputting to the MLM values of a given test and those of tests earlier in the sequence while masking those later in the sequence, (ii) computing probabilities of test failures for the masked tests found later in the sequence than the given test, and (iii) applying the PFIs of test results later in the sequence than the given test as ground-truths to update parameters of the MLM.

Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by replacing one or more of the data transformation elements in the hardware design with a function element which is treated as an unevaluated function of its combinational inputs by a formal verification tool such that during formal verification the function element will produce the same output for the same inputs, and formally verifying that for each transaction of a set of transactions an instantiation of the modified hardware design for the data transformation pipeline produces a set of one or more outputs that matches a reference set of one or more outputs for that transaction.

An integrated circuit (IC) device and a method for communicating test data utilizes test control circuitry, and a test controller. The test controller is coupled with the test control circuitry and decodes packetized test pattern data to identify configuration data for the test controller and test data for the test control circuitry. The test controller further communicates the test data to the test control circuitry, and packetizes resulting data received from the test control circuitry. The resulting data corresponds to errors identified by a test performed based on the test pattern data.

This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

A system for testing antenna-in-package (AiP) modules and a method for using the same is disclosed. Firstly, AiP modules respectively receive RF signals from a testing transmitting antenna. Then, at least one of the power and the phase of each of the RF signals is adjusted to generate modulated RF amplified signals as recognition tags with difference. The RF amplified signals are received from each control integrated circuit (IC) and the power of the modulated RF amplified signals is summed to generate a net mixed test signal. Finally, the test signal is received and RF properties corresponding to at least one of the power and the phase of each of the RF amplified signals as recognition tags are obtained. The method can simultaneously test a plurality of AiP modules to shorten the test time.

A system for testing antenna-in-package (AiP) modules and a method for using the same is disclosed. Firstly, AiP modules respectively receive RF signals from a testing transmitting antenna. Then, at least one of the power and the phase of each of the RF signals is adjusted to generate modulated RF amplified signals as recognition tags with difference. The RF amplified signals are received from each control integrated circuit (IC) and the power of the modulated RF amplified signals is summed to generate a net mixed test signal. Finally, the test signal is received and RF properties corresponding to at least one of the power and the phase of each of the RF amplified signals as recognition tags are obtained. The method can simultaneously test a plurality of AiP modules to shorten the test time.