The exemplary embodiments of the present invention provides a scan cluster reordering method and apparatus which perform a scan correlation aware scan cluster reordering to reduce a power generated during the scan test and place scan cells having a high correlation to be adjacent to each other by analyzing the correlation between scan cells, and reduce a test power generated during the scan test.

Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.

An integrated circuit includes a data propagation path including a flip-flop. The flip-flop includes a first latch and a second latch. The integrated circuit includes a third latch that acts as a dummy latch. The input of the third latch is coupled to the output of the first latch. The integrated circuit includes a fault detector coupled to the output of the flip-flop and the output of the third latch. The third latch includes a signal propagation delay selected so that the third latch will fail to capture data in a given clock cycle before the second latch of the flip-flop fails to capture the data in the given clock cycle. The fault detector that detects when the third latch is failed to capture the data.

A test system of embodiments electrically connects one or more first semiconductor chips formed on a first wafer and one or more second semiconductor chips formed on a second wafer to perform tests on the one or more first and second semiconductor chips. The test system includes a test device that supplies a test signal to each of the one or more first semiconductor chips, a first probe device including a first probe to be connected to a first internal pad of each of the one or more first semiconductor chips and a first communication circuit configured to transmit and receive a signal, and a second probe device including a second probe to be connected to a second internal pad of each of the one or more second semiconductor chips and a second communication circuit configured to transmit and receive the signal to and from the first communication circuit.

A boundary scan test method and a storage medium are disclosed. The method can be capable of testing the connectivity of a pad having a direct connection to user logic. The method is preformed based on a scan test instruction to FPGA. According to the method of the invention, software configuration is performed in FPGA user logic with respect to a PAD to be tested, such that the PAD can be tested according to the configuration without the need to test or pass through PADs that do not need to be tested. The method shortens boundary scan chains, thereby enabling rapid and flexible boundary scan tests and improving test efficiency.

A method of updating firmware in a chip in a stable and effective manner receives firmware outputted by a controller. The received firmware is burned into the chip. A voltage level of a controlling signal outputted by a controlling pin of the chip is latched to a certain level based on a latching signal at a first voltage level outputted by the controller. The storage medium is refreshed for making the burned firmware effective based on refresh instruction outputted by the controller. The latching signal at a second voltage level for unlatching the voltage level of the controlling signal is outputted by the controller if operations of the chip are stable. An updating operation of the chip by the method does not interrupt other operations being executed by the chip. A firmware updating apparatus and a computer readable storage medium applying the method are also disclosed.

Example embodiments are disclosed of systems and methods for predicting failure probabilities of future product tests of a testing sequence based on outcomes of prior tests. Predictions are made by a machine-learning-based model (MLM) trained with a set of test-result sequence records (TRSRs) including test values and pass/fail indicators (PRIs) of completed tests. Within training epochs over the set, iterations are carried out over each TRSR. Each iteration involves sub-iterations carried out successively over test results of the TRSR. Each sub-iteration involves (i) inputting to the MLM values of a given test and those of tests earlier in the sequence while masking those later in the sequence, (ii) computing probabilities of test failures for the masked tests found later in the sequence than the given test, and (iii) applying the PFIs of test results later in the sequence than the given test as ground-truths to update parameters of the MLM.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

An electronic device includes a processing unit with a memory, a JTAG interface with test-data-input and test-mode-select lines coupled to the processing unit, a bridge circuit, and a multiplexer circuit. The bridge circuit includes a serial communication interface receiving a serial data input signal which conveys an input serial data frame. The bridge circuit includes a serial-to-parallel converter circuit block receiving the input serial data frame, processing the input serial data frame to read first and second subsets of input binary values therefrom, and transmitting the first subset via a first output signal and the second subset via a second output signal. The multiplexer circuit selectively propagates a received test-data-input signal or the first output signal to the test data input line, and selectively propagates a test-mode-select signal or the second output signal to the test mode select line of the JTAG interface.