Testing clock division circuitry includes generating pseudo random test pattern bits for scan chain logic in programmable clock division logic circuitry and divided clock counter circuitry. A shift clock is used to shift the test pattern bits into the scan chain logic. A capture clock signal is used in the programmable clock division logic during a non-test mode of operation. The shift clock is used to provide output shift bits from the scan chain logic to a multi-input shift register (MISR). Once all the output shift bits for the test pattern bits are provided to the MISR, a final test signature from the MISR is compared to an expected test signature to determine whether the programmable clock division logic circuitry and divided clock counter circuitry are free of faults.

Testing clock division circuitry includes generating pseudo random test pattern bits for scan chain logic in programmable clock division logic circuitry and divided clock counter circuitry. A shift clock is used to shift the test pattern bits into the scan chain logic. A capture clock signal is used in the programmable clock division logic during a non-test mode of operation. The shift clock is used to provide output shift bits from the scan chain logic to a multi-input shift register (MISR). Once all the output shift bits for the test pattern bits are provided to the MISR, a final test signature from the MISR is compared to an expected test signature to determine whether the programmable clock division logic circuitry and divided clock counter circuitry are free of faults.

A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

The disclosure describes an apparatus for testing a component, wherein the apparatus is configured to apply a magnetic field with a magnetic field orientation from a set of magnetic field orientations to the component. The apparatus is further configured to perform a test on the component in the presence of the respective magnetic fields with the respective magnetic field orientations from the set of magnetic field orientations to obtain an information characterizing an operation of the component. The apparatus is also configured to determine a test result based on the information characterizing the operation of the component in the presence of different magnetic fields with different magnetic field orientations from the set of magnetic field orientations. The disclosure also describes a method of testing and a computer-readable storage device for implementing the method and provides more efficiency in view of reliability and costs.

Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

A multi-lane transmitting apparatus includes lanes, and each lane includes a serializer circuit to convert parallel bits to serial bits. A clock signal generator generates a first clock signal having phases. A deserializer circuit converts serial bits to parallel bits. A Built-In Self-Test (BIST) circuit includes a signal generator circuit for generating a signal having bits in a defined pattern. A comparator circuit compares a pattern of bits of an output signal with the defined pattern. A BIST lane circuit monitors a status of the lanes. A BIST central circuit receives the status and determines if a number of lanes having an unmatched status is less than a threshold value. A phase extrapolator circuit adjusts a phase of the first clock signal when the number of the lanes is less than the threshold value.

Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Test stimulus signals applied to at least one circuit under test are produced in a set of test stimulus generators as a function of test stimulus information loaded in test stimulus registers. Loading of the test stimulus information in the test stimulus registers is controlled as a function of test programming information loaded via a programming interface in a respective control register in a set of control registers. The test stimulus generators are activated as a function of the test programming information loaded in said control registers. Test outcome signals received from the at least one circuit under test are used to produce signature comparison signals, which are compared with respective programmable signature reference signals stored in a set of input signature registers, are produced in response to the signature comparison signals produced from the test outcome signals failing to match with the respective reference signals.