Structures for a photodetector or terminator and methods of fabricating a structure for a photodetector or terminator. The structure includes a waveguide core, a light-absorbing layer having a sidewall, and a taper positioned adjacent to the sidewall of the light-absorbing layer. The taper extends laterally from the sidewall of the light-absorbing layer to overlap with the waveguide core, and the taper has a thickness that varies with position relative to the sidewall of the light-absorbing layer. For example, the thickness of the taper may decrease with increasing distance from the sidewall of the light-absorbing layer.

A device includes a photonic routing structure including a silicon waveguide, photonic devices, and a grating coupler, wherein the silicon waveguide is optically coupled to the photonic devices and to the grating coupler; an interconnect structure on the photonic routing structure, wherein the grating coupler is configured to optically couple to an external optical fiber disposed over the interconnect structure; and computing sites on the interconnect structure, wherein each computing site includes an electronic die bonded to the interconnect structure, wherein each electronic die of the computing sites is electrically connected to a corresponding photonic device of the photonic devices.

Disclosed is a compact on-chip polarization splitter-rotator based on a Bezier curve gradient waveguide. The Bezier curve gradient waveguide structure is a standard SOI-based wafer structure, comprising a substrate, of which the bottom layer is buried with oxide (SiO.sub.2), and the top is composed of silicon waveguides, including a common output waveguide and a specially-structured waveguide containing Bessel curve boundaries. The common waveguide structure is composed of a cuboid waveguide, and the specially-structured waveguide is composed of an input region, an output region, a width-gradient waveguide (Bezier curve gradient structure) and a coupling region, where a width of the gradient waveguide is determined by a third-order Bezier curve, and the coupling region is composed of two asymmetrical waveguide regions.

A photonic integrated circuit (PIC) includes one or more couplers to interface a light source with the PIC, a splitter directly coupled to the one or more couplers at a coupling point of the PIC, a modulator to receive light from the couplers, and a connecting waveguide to connect the splitter to the modulator. The waveguide may be a rib waveguide. The PIC may be integrated with devices such as a CWDM or a PSM device, and may provide improved performance and lower attention for high optical power applications.

A mirror and method of fabricating the mirror, the method comprising: providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; creating a via in the silicon device layer, the via extending to the BOX layer; etching away a portion of the BOX layer starting at the via and extending laterally away from the via in a first direction to create a channel between the silicon device layer and silicon support layer; applying an anisotropic etch via the channel to regions of the silicon device layer and silicon support layer adjacent to the channel; the anisotropic etch following an orientation plane of the silicon device layer and silicon support layer to create a cavity underneath an overhanging portion of the silicon device layer; the overhanging portion defining a planar underside surface for vertically coupling light into and out of the silicon device layer; and applying a metal coating to the underside surface.

In integrated optical structures (e.g., silicon-to-silicon-nitride mode converters) implemented in semiconductor-on-insulator substrates, wire waveguides whose sidewalls substantially consist of portions coinciding with crystallographic planes and do not extend laterally beyond the top surface of the wire waveguide may provide benefits in performance and/or manufacturing needs. Such wire waveguides may be manufactured, e.g., using a dry-etch of the semiconductor device layer down to the insulator layer to form a wire waveguide with exposed sidewalls, followed by a smoothing crystallographic wet etch.

A structure of a silicon photonics device for LIDAR includes a first insulating structure and a second insulating structure disposed above one or more etched silicon structures overlying a substrate member. A metal layer is disposed above the first insulating structure without a prior deposition of a diffusion barrier and adhesion layer. A thin insulating structure is disposed above the second insulating structure. A first configuration of the metal layer, the first insulating structure and the one or more etched silicon structures forms a free-space coupler. A second configuration of the thin insulating structure above the second insulating structure forms an edge coupler.

An optical sensing module suitable for wearable devices, the optical sensing module comprising: a silicon or silicon nitride transmitter photonic integrated circuit (PIC), the transmitter PIC comprising: a plurality of lasers, each laser of the plurality of lasers operating at a wavelength that is different from the wavelength of the others; an optical manipulation region, the optical manipulation region comprising one or more of: an optical modulator, optical multiplexer (MUX); and additional optical manipulation elements; and one or more optical outputs for light originating from the plurality of lasers.

IC chip package with silicon photonic features integrated onto an interposer along with electrical routing redistribution layers. An active side of an IC chip may be electrically coupled to a first side of the interposer through first-level interconnects. The interposer may include a core (e.g., of silicon or glass) with electrical through-vias extending through the core. The redistribution layers may be built up on a second side of the interposer from the through-vias and terminating at interfaces suitable for coupling the package to a host component through second-level interconnects. Silicon photonic features (e.g., of the type in a photonic integrated circuit chip) may be fabricated within a silicon layer of the interposer using high temperature processing, for example of 350° C., or more. The photonic features may be fabricated prior to the fabrication of metallized redistribution layers, which may be subsequently built-up within dielectric material(s) using lower temperature processing.

The present disclosure provides a semiconductor device package. The semiconductor device package includes a semiconductor substrate having a first surface and a first optical coupler disposed on the first surface of the semiconductor substrate. The first optical coupler includes a first surface facing away from the first surface of the semiconductor substrate and a first lateral surface connected to the first surface of the first optical coupler. The first surface of the first optical coupler and the first lateral surface of the optical coupler define an angle greater than 90 degrees. A method of manufacturing a semiconductor device package is also disclosed.