An embodiment photodetector includes a clad layer formed on a substrate, a first semiconductor layer formed on the clad layer, and a second semiconductor layer and a third semiconductor layer with the first semiconductor layer interposed therebetween formed on the clad layer. The photodetector includes a light absorbing layer made of an n-type III-V compound semiconductor formed on the first semiconductor layer through an insulating layer.

An integrated microwave photonics (IMWP) apparatus is provided using sapphire as a platform. The IMWP apparatus includes: a sapphire substrate having a step-terrace surface; and a III-V stack layer epitaxially grown on the sapphire substrate. The III-V stack layer includes: a first III-V layer disposed on the sapphire substrate; a low temperature (LT) III-V buffer layer disposed on the first III-V layer; multiple second III-V layers disposed and stacked on the LT III-V buffer layer; a third III-V layer disposed on the second III-V layers; a III-V quantum well layer disposed on the third III-V layers; and a fourth III-V layer disposed on the III-V quantum well layer. The second III-V layers are respectively annealed. A growth temperature of the LT III-V layer and a growth temperature of the III-V quantum well layer are lower than a growth temperature of each of the first, second, third and fourth III-V layers.

A device includes three elements fabricated on a common substrate. The first element includes an active waveguide structure having at least three sub-layers supporting a first optical mode. The second element has a passive waveguide structure supporting a second optical mode, and the third element, butt-coupled to the first element, has an intermediate waveguide structure supporting intermediate optical modes. One sub-layer in the active waveguide structure includes an n-contact layer, another sub-layer includes a p-contact layer, and a third sub-layer includes an active region. A tapered waveguide structure in at least one of the second and third elements facilitates efficient adiabatic transformation between the second optical mode and an intermediate optical mode. No adiabatic transformation occurs between that intermediate optical mode and the first optical mode. Mutual alignments of the three elements are defined using lithographic alignment marks that facilitate precise alignment between layers formed fabrication of the elements.

A laser integrated photonic platform to allow for independent fabrication and development of laser systems in silicon photonics. The photonic platform includes a silicon substrate with an upper surface, one or more through silicon vias (TSVs) defined through the silicon substrate, and passive alignment features in the substrate. The photonic platform includes a silicon substrate wafer with through silicon vias (TSVs) defined through the silicon substrate, and passive alignment features in the substrate for mating the photonic platform to a photonics integrated circuit. The photonic platform also includes a III-V semiconductor material structure wafer, where the III-V wafer is bonded to the upper surface of the silicon substrate and includes at least one active layer forming a light source for the photonic platform.

A method of manufacturing a III-V based optoelectronic device on a silicon-on-insulator wafer. The silicon-on-insulator wafer comprises a silicon device layer, a substrate, and an insulator layer between the substrate and silicon device layer. The method includes the steps of: providing a device coupon, the device coupon being formed of a plurality of III-V based layers; providing the silicon-on-insulator wafer, the wafer including a cavity with a bonding region; transfer printing the device coupon into the cavity, and bonding a layer of the device coupon to the bonding region, such that a channel is left around one or more lateral sides of the device coupon; filling the channel with a bridge-waveguide material; and performing one or more etching steps on the device coupon, silicon-on-insulator wafer, and/or channel.

A device includes three elements fabricated on a common substrate. The first element includes an active waveguide structure having at least three sub-layers supporting a first optical mode. The second element has a passive waveguide structure supporting a second optical mode, and the third element, butt-coupled to the first element, has an intermediate waveguide structure supporting intermediate optical modes. One sub-layer in the active waveguide structure includes an n-contact layer, another sub-layer includes a p-contact layer, and a third sub-layer includes an active region. A tapered waveguide structure in at least one of the second and third elements facilitates efficient adiabatic transformation between the second optical mode and an intermediate optical mode. No adiabatic transformation occurs between that intermediate optical mode and the first optical mode. Mutual alignments of the three elements are defined using lithographic alignment marks that facilitate precise alignment between layers formed fabrication of the elements.

This disclosure provides photonic integrated chip that has an optical waveguide located on a photonic circuit substrate that includes a photonic circuit that is optically coupled to the waveguide. A microfluidic channel is in a silicon substrate and is attached to the photonic circuit substrate. The microfluidic channel is positioned over the optical waveguide such that its side surfaces and an outermost surface extend into the microfluidic channel. The microfluidic channel extends along a length of the optical waveguide, and nanoparticles are located on or adjacent the optical waveguide located within the microfluidic channel.

A semiconductor structure for a photonic integrated circuit, comprising: a substrate; a waveguide on the substrate; a passive region comprising a first cladding layer in contact with a first portion of the waveguide; and an active region comprising a second cladding layer different to the first cladding layer, the second cladding layer in contact with a second portion of the waveguide and the first cladding layer. There is a photonic integrated circuit comprising the semiconductor structure. There is a method of manufacturing a semiconductor structure for a photonic integrated circuit.

An electro-optically active device comprising: a silicon on insulator (SOI) substrate including a silicon base layer, a buried oxide (BOX) layer on top of the silicon base layer, a silicon on insulator (SOI) layer on top of the BOX layer, and a substrate cavity which extends through the SOI layer, the BOX layer and into the silicon base layer, such that a base of the substrate cavity is formed by a portion of the silicon base layer; an electro-optically active waveguide including an electro-optically active stack within the substrate cavity; and a buffer region within the substrate cavity beneath the electro-optically active waveguide, the buffer region comprising a layer of Ge and a layer of GaAs.

A method of manufacturing an optoelectronic device. The manufactured device includes a photonic component coupled to a waveguide. The method comprising: providing a device coupon, the device coupon including the photonic component; providing a silicon platform, the silicon platform comprising a cavity within which is a bonding surface for the device coupon; transfer printing the device coupon onto the cavity, such that a surface of the device coupon directly abuts the bonding surface and at least one channel is present between the device coupon and a sidewall of the cavity; and filling the at least one channel with a filling material via a spin-coating process, to form a bridge coupling the III-V semiconductor based photonic component to the silicon waveguide.