A device comprises first, second and third elements fabricated on a common substrate. The first element comprises an active waveguide structure comprising: one portion, of effective cross-sectional area A1, supporting a first optical mode; and a second portion, butt-coupled to the first portion, of effective cross-sectional area A2>A1. The second element comprises a passive waveguide structure supporting a second optical mode. The third element, at least partly butt-coupled to the second portion, comprises an intermediate waveguide structure supporting intermediate optical modes. If the first optical mode differs from the second optical mode by more than a predetermined amount, a tapered waveguide structure in at least one of the second and third elements facilitates efficient adiabatic transformation between the first optical mode and one intermediate optical mode. No adiabatic transformation occurs between any intermediate optical mode and the first optical mode. Mutual alignments of the elements are defined using lithographic marks.

Hybrid optical integration places very strict manufacturing tolerances and performance requirements upon the multiple elements to exploit passive alignment techniques as well as having additional processing requirements. Alternatively, active alignment and soldering/fixing where feasible is also complex and time consuming with 3, 4, or 6-axis control of each element. However, microelectromechanical (MEMS) systems can sense, control, and activate mechanical processes on the micro scale. Beneficially, therefore the inventors combine silicon MEMS based micro-actuators with silicon CMOS control and drive circuits in order to provide alignment of elements within a silicon optical circuit either with respect to each other or with other optical elements hybridly integrated such as compound semiconductor elements. Such inventive MEMS based circuits may be either maintained as active during deployment or powered off once the alignment has been “locked” through an attachment/retention/latching process.

A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region, a silicon device on the substrate extension layer in a second region, a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region, and a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device.

An electro-optically active device comprising: a silicon on insulator (SOI) substrate including a silicon base layer, a buried oxide (BOX) layer on top of the silicon base layer, a silicon on insulator (SOI) layer on top of the BOX layer, and a substrate cavity which extends through the SOI layer, the BOX layer and into the silicon base layer, such that a base of the substrate cavity is formed by a portion of the silicon base layer; an electro-optically active waveguide including an electro-optically active stack within the substrate cavity; and a buffer region within the substrate cavity beneath the electro-optically active waveguide, the buffer region comprising a layer of Ge and a layer of GaAs.

A semiconductor layer formed on a clad layer and a light absorbing layer formed on the semiconductor layer are provided. The semiconductor layer includes a p-type region and an n-type region. The p-type region, which is of p-type, is provided on a side of one side portion of the light absorbing layer in a direction perpendicular to a direction in which light is guided, and the n-type region, which is of n-type, is provided on a side of another side portion of the light absorbing layer in the direction perpendicular to the direction in which light is guided. A p-type contact layer, which is of p-type, is formed on the p-type region, and an n-type contact layer is formed on the n-type region.

Embodiments of the invention are directed to a method of fabrication of an electro-optical device. A non-limiting example of the method relies on a waveguide. A trench is opened in the waveguide and a stack of optically active semiconductor materials is directly grown from a bottom wall of the trench and are stacked along a stacking direction that is perpendicular to a main plane of the waveguide. The stack is partly encapsulated in the waveguide, whereby a bottom layer of the stack is in direct contact with a waveguide core material, whereas upper portions of opposite, lateral sides of the stack are exposed. An insulating layer of material is deposited to cover exposed surfaces of the waveguide and structured to form a lateral growth template. Contact layers are laterally grown due to the lateral growth template formed. The contact layers can include an n-doped and p-doped contact layers.

A laser integrated photonic platform to allow for independent fabrication and development of laser systems in silicon photonics. The photonic platform includes a silicon substrate with an upper surface, one or more through silicon vias (TSVs) defined through the silicon substrate, and passive alignment features in the substrate. The photonic platform includes a silicon substrate wafer with through silicon vias (TSVs) defined through the silicon substrate, and passive alignment features in the substrate for mating the photonic platform to a photonics integrated circuit. The photonic platform also includes a III-V semiconductor material structure wafer, where the III-V wafer is bonded to the upper surface of the silicon substrate and includes at least one active layer forming a light source for the photonic platform.

This disclosure provides photonic integrated chip that has an optical waveguide located on a photonic circuit substrate that includes a photonic circuit that is optically coupled to the waveguide. A microfluidic channel is in a silicon substrate and is attached to the photonic circuit substrate. The microfluidic channel is positioned over the optical waveguide such that its side surfaces and an outermost surface extend into the microfluidic channel. The microfluidic channel extends along a length of the optical waveguide, and nanoparticles are located on or adjacent the optical waveguide located within the microfluidic channel.

A photonic integrated circuit may include a substrate and an optical waveguide integrated with the substrate. The optical waveguide may include a bend section, wherein a bend shape of the bend section is defined by a curvature function to suppress waveguide mode conversion.

The present disclosure relates to a method for growing III-V compound semiconductors on silicon-on-insulators. Starting from {111}-oriented Si seed surfaces between a buried oxide layer and a patterned mask layer, the III-V compound semiconductor is grown within lateral trenches by metal organic chemical vapor deposition such that the non-defective portion of the III-V compound semiconductor formed on the buried oxide layer is substantially free of crystalline defects and has high crystalline quality.