G02B6/1221

Fabrication method of high aspect ratio solder bumping with stud bump and injection molded solder, and flip chip joining with the solder bump

A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.

Optical Connection Structure and Method for Forming Same
20210356669 · 2021-11-18 ·

A first optical waveguide layer and a second optical waveguide layer are optically connected by a resin optical waveguide composed of a resin core composed of a light-transmitting resin and a cladding composed of air surrounding the resin core. A hollow outer wall structure that houses the resin optical waveguide is provided. An enclosed space is provided inside the outer wall structure. The outer wall structure is disposed to bridge the gap between the first optical device and the second optical device.

Diffusion controlled nanocomposite-inks

A method of manufacturing a nanocomposite GRIN optical-element. The method comprises providing a volumetric gradient refractive profile and providing a plurality of nanocomposite-inks to form the GRIN optical-element. Each of the plurality of nanocomposite-inks have nanoparticles dispersed in an organic-matrix. The plurality of nanocomposite-inks comprising of a nanoparticle diffusion inhibiting nanocomposite-ink wherein nanoparticle diffusion is inhibited with respect to another of the plurality of nanocomposite-inks. The diffusion inhibiting nanocomposite-ink having a different dielectric property from at least one of the other plurality of nanocomposite-inks. The plurality of nanocomposite-inks also comprising a nanoparticle diffusion permitting nanocomposite-ink wherein nanoparticle diffusion is permitted with respect to at least another of the plurality of nanocomposite-inks.

OPTICAL AND THERMAL INTERFACE FOR PHOTONIC INTEGRATED CIRCUITS
20220003945 · 2022-01-06 ·

Described herein are photonic systems and devices including a optical interface unit disposed on a bottom side of a photonic integrated circuit (PIC) to receive light from an emitter of the PIC. A top side of the PIC includes a flip-chip interface for electrically coupling the PIC to an organic substrate via the top side. An alignment feature corresponding to the emitter is formed with the emitter to be offset by a predetermined distance value; because the emitter and the alignment feature are formed using a shared processing operation, the offset (i.e., predetermined distance value) may be precise and consistent across similarly produced PICs. The PIC comprises a processing feature to image the alignment feature from the bottom side (e.g., a hole). A heat spreader layer surrounds the optical interface unit and is disposed on the bottom side of the PIC to spread heat from the PIC.

Optical and thermal interface for photonic integrated circuits

Described herein are photonic systems and devices including a optical interface unit disposed on a bottom side of a photonic integrated circuit (PIC) to receive light from an emitter of the PIC. A top side of the PIC includes a flip-chip interface for electrically coupling the PIC to an organic substrate via the top side. An alignment feature corresponding to the emitter is formed with the emitter to be offset by a predetermined distance value; because the emitter and the alignment feature are formed using a shared processing operation, the offset (i.e., predetermined distance value) may be precise and consistent across similarly produced PICs. The PIC comprises a processing feature to image the alignment feature from the bottom side (e.g., a hole). A heat spreader layer surrounds the optical interface unit and is disposed on the bottom side of the PIC to spread heat from the PIC.

Athermal silicon optical add-drop multiplexers based on thermo-optic coefficient tuning of sol-gel material

An athermal optical waveguide structure such as an optical add drop multiplexer (OADM) or the like is fabricated by a method that includes forming a lower cladding layer on a substrate. A waveguiding core layer is formed on the lower cladding layer. An upper cladding layer is formed on the waveguiding core layer and the lower cladding layer a sol-gel material. The sol-gel material includes an organically modified siloxane and a metal oxide. A thermo-optic coefficient of the sol-gel material is adjusted by curing the sol-gel material for a selected duration of time at a selected temperature such that the thermo-optic coefficient of the sol-gel material compensates for a thermo-optic coefficient of at least the waveguiding core layer such that an effective thermo-optic coefficient of the optical waveguide structure at a specified optical wavelength and over a specified temperature range is reduced.

BIASED TOTAL THICKNESS VARIATIONS IN WAVEGUIDE DISPLAY SUBSTRATES
20230026965 · 2023-01-26 ·

A plurality of waveguide display substrates, each waveguide display substrate having a cylindrical portion having a diameter and a planar surface, a curved portion opposite the planar surface defining a nonlinear change in thickness across the substrate and having a maximum height D with respect to the cylindrical portion, and a wedge portion between the cylindrical portion and the curved portion defining a linear change in thickness across the substrate and having a maximum height W with respect to the cylindrical portion. A target maximum height D.sub.t of the curved portion is 10.sup.-7 to 10.sup.-6 times the diameter, D is between about 70% and about 130% of D.sub.t, and W is less than about 30% of D.sub.t.

STRUCTURES AND PROCESS FLOW FOR INTEGRATED PHOTONIC-ELECTRIC IC PACKAGE BY USING POLYMER WAVEGUIDE

Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.

Flexible photonic skin

A flexible photonic skin is provided, including a functional layer, an adhesive layer used for fixing the functional layer and made of hypoallergenic polyvinyl ethyl ether, and a packaging layer made of a polyurethane semi-transparent film and adhered to the adhesive layer, which are arranged successively from the top down, wherein the functional layer consists of two electrodes located on two sides and used for acquiring electrocardiographic signals of a human body, and a polymer-based photonic integrated chip located between the two electrodes and used for acquiring body temperature, pulse, blood pressure and blood glucose signals of the human body; and, the polymer-based photonic integrated chip processes and outputs the acquired electrocardiographic signals of the human body as well as the body temperature, pulse, blood pressure and blood glucose signals of the human body.

Semiconductor package and manufacturing method thereof

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. The encapsulant laterally encapsulates the photonic die. The wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.