A 2-D sensor array includes a semiconductor substrate and a plurality of pixels disposed on the semiconductor substrate. Each pixel includes a coupling region and a junction region, and a slab waveguide structure disposed on the semiconductor substrate and extending from the coupling region to the region. The slab waveguide includes a confinement layer disposed between a first cladding layer and a second cladding layer. The first cladding and the second cladding each have a refractive index that is lower than a refractive index of the confinement layer. Each pixel also includes a coupling structure disposed in the coupling region and within the slab waveguide. The coupling structure includes two materials having different indices of refraction arranged as a grating defined by a grating period. The junction region comprises a p-n junction in communication with electrical contacts for biasing and collection of carriers resulting from absorption of incident radiation.

A 2-D sensor array includes a semiconductor substrate and a plurality of pixels disposed on the semiconductor substrate. Each pixel includes a coupling region and a junction region, and a slab waveguide structure disposed on the semiconductor substrate and extending from the coupling region to the region. The slab waveguide includes a confinement layer disposed between a first cladding layer and a second cladding layer. The first cladding and the second cladding each have a refractive index that is lower than a refractive index of the confinement layer. Each pixel also includes a coupling structure disposed in the coupling region and within the slab waveguide. The coupling structure includes two materials having different indices of refraction arranged as a grating defined by a grating period. The junction region comprises a p-n junction in communication with electrical contacts for biasing and collection of carriers resulting from absorption of incident radiation.

Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.

Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.

Processes and apparatuses described herein reduce the manufacturing time, the cost of parts, and the cost of assembly per laser for photonic interconnects incorporated into computing systems. An output side of a laser assembly is placed against an input side of a silicon interposer (SiP) such that each pad in a plurality of pads positioned on the output side of the laser assembly is in contact with a respective solder bump that is also in contact with a corresponding pad positioned on the input side of the SiP. The laser assembly is configured to emit laser light from the output side into an input grating of the SiP. The solder bumps are heated to a liquid phase. Capillary forces of the solder bumps realign the laser assembly and the SiP while the solder bumps are in the liquid phase. The solder bumps are then allowed to cool.

Processes and apparatuses described herein reduce the manufacturing time, the cost of parts, and the cost of assembly per laser for photonic interconnects incorporated into computing systems. An output side of a laser assembly is placed against an input side of a silicon interposer (SiP) such that each pad in a plurality of pads positioned on the output side of the laser assembly is in contact with a respective solder bump that is also in contact with a corresponding pad positioned on the input side of the SiP. The laser assembly is configured to emit laser light from the output side into an input grating of the SiP. The solder bumps are heated to a liquid phase. Capillary forces of the solder bumps realign the laser assembly and the SiP while the solder bumps are in the liquid phase. The solder bumps are then allowed to cool.

A grating coupler is disclosed. The grating coupler comprises a grating formed in a waveguide formed in a silicon layer of a silicon on insulator photonic component. The grating has a series of sequentially arranged grating elements i, each comprising an alternating etched trench section having a length L.sub.e and an etch depth e, and an unetched tooth section having a length L.sub.0. Each grating element has a total length of .sub.i and a fill factor F.sub.i. The fill factor F.sub.i of each grating element varies across the grating coupler according to an apodization function dependent on the location of the grating element. The total length of each grating element .sub.i varies across the grating coupler such that the effective refractive index of each grating element causes the Bragg condition to be satisfied for all of the grating elements of the grating.

Disclosed is a system and method for communication using an efficient fiber-to-chip grating coupler with a high coupling efficiency. In one embodiment, a method for communication, includes: transmitting optical signals between a semiconductor photonic die on a substrate and an optical fiber array attached to the substrate using at least one corresponding grating coupler on the semiconductor photonic die, wherein the at least one grating coupler each comprises a plurality of coupling gratings, a waveguide, a cladding layer, a first reflection layer and a second reflection layer, wherein the plurality of coupling gratings each comprises at least one step in a first lateral direction and extends in a second lateral direction, wherein the first and second lateral directions are parallel to a surface of the substrate and perpendicular to each other in a grating plane, wherein the first reflection layers are configured such that the plurality of coupling gratings is disposed between the first reflection layer and the cladding layer, wherein the second reflection layer are configured such that the cladding layer is disposed between the second reflection layer and the waveguide.

The systems and methods discussed herein are for the fabrication of diffraction gratings, such as those gratings used in waveguide combiners. The waveguide combiners discussed herein are fabricated using nanoimprint lithography (NIL) of high-index and low-index materials in combination with and directional etching high-index and low-index materials. The waveguide combiners can be additionally or alternatively formed by the directional etching of transparent substrates. The waveguide combiners that include diffraction gratings discussed herein can be formed directly on permanent transparent substrates. In other examples, the diffraction gratings can be formed on temporary substrates and transferred to a permanent, transparent substrate.

A method includes forming silicon waveguide sections in a first oxide layer over a substrate, the first oxide layer disposed on the substrate, forming a routing structure over the first oxide layer, the routing structure including one or more insulating layers and one or more conductive features in the one or more insulating layers, recessing regions of the routing structure, forming nitride waveguide sections in the recessed regions of the routing structure, wherein the nitride waveguide sections extend over the silicon waveguide sections, forming a second oxide layer over the nitride waveguide sections, and attaching semiconductor dies to the routing structure, the dies electrically connected to the conductive features.