A method includes forming silicon waveguide sections in a first oxide layer over a substrate, the first oxide layer disposed on the substrate, forming a routing structure over the first oxide layer, the routing structure including one or more insulating layers and one or more conductive features in the one or more insulating layers, recessing regions of the routing structure, forming nitride waveguide sections in the recessed regions of the routing structure, wherein the nitride waveguide sections extend over the silicon waveguide sections, forming a second oxide layer over the nitride waveguide sections, and attaching semiconductor dies to the routing structure, the dies electrically connected to the conductive features.

Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.

Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.

Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.

Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.

A III-V optoelectronic light emitting device is epitaxially formed on a semiconductor on insulator substrate over a buried waveguide core. The device is optically coupled to the underlying waveguide core. A MOSFET device is formed on a semiconductor substrate beneath the insulator that contains the waveguide core.

A III-V optoelectronic light emitting device is epitaxially formed on a semiconductor on insulator substrate over a buried waveguide core. The device is optically coupled to the underlying waveguide core. A MOSFET device is formed on a semiconductor substrate beneath the insulator that contains the waveguide core.

An optical coupler has a waveguide coupled to a grating of multiple scattering units, each scattering unit having a first scattering element formed of a shape in a polysilicon gate layer and a second scattering element formed of a shape in a body silicon layer of a metal-oxide-semiconductor (MOS) integrated circuit (IC). The couplers may be used in a system having a coupler on each of a first and second IC, infrared light being formed into a beam passing between the couplers. Vias may be interposed in third ICs between the first and second ICs. The couplers may be configured with nonuniform width of scattering elements to produce Gaussian or focused beams.

An optical coupler has a waveguide coupled to a grating of multiple scattering units, each scattering unit having a first scattering element formed of a shape in a polysilicon gate layer and a second scattering element formed of a shape in a body silicon layer of a metal-oxide-semiconductor (MOS) integrated circuit (IC). The couplers may be used in a system having a coupler on each of a first and second IC, infrared light being formed into a beam passing between the couplers. Vias may be interposed in third ICs between the first and second ICs. The couplers may be configured with nonuniform width of scattering elements to produce Gaussian or focused beams.

A photonic chip includes a device layer and a port layer, with an optical port located at the port layer. Inter-layer optical couplers are provided for coupling light between the device and port layers. The inter-layer couplers may be configured to couple signal light but block pump light or other undesired wavelength from entering the device layer, operating as an input filter. The port layer may accommodate other light pre-processing functions, such as optical power splitting, that are undesirable in the device layer.