Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a first doped region having a first doping type disposed in a semiconductor substrate. A second doped region having a second doping type different than the first doping type is disposed in the semiconductor substrate and laterally spaced from the first doped region. A waveguide structure is disposed in the semiconductor substrate and laterally between the first doped region and the second doped region. A photodetector is disposed at least partially in the semiconductor substrate and laterally between the first doped region and the second doped region. The waveguide structure is configured to guide one or more photons into the photodetector. The photodetector has an upper surface that continuously arcs between opposite sidewalls of the photodetector. The photodetector has a lower surface that continuously arcs between the opposite sidewalls of the photodetector.

A method of manufacturing a photonic chip. The method comprises providing a wafer comprising a silicon substrate, and a low refractive index layer above the silicon substrate, forming a first trench having a first height and a second trench having a second height by etching the low refractive index layer. The second height is greater than the first height and the second trench has a bottom surface that is closer to the substrate than a bottom surface of the first trench.

A photonic integrated circuit (PIC) includes a semiconductor substrate, one or more passive components, and one or more active components. The one or more passive components are fabricated on the semiconductor substrate, wherein the passive components are fabricated in a III-V type semiconductor layer. The one or more active components are fabricated on top of the one or more passive components, wherein optical signals are communicated between the one or more active components via the one or more passive components.

A method includes etching a silicon layer to form a silicon slab and an upper silicon region over the silicon slab, and implanting the silicon slab and the upper silicon region to form a p-type region, an n-type region, and an intrinsic region between the p-type region and the n-type region. The method further includes etching the p-type region, the n-type region, and the intrinsic region to form a trench. The remaining portions of the upper silicon region form a Multi-Mode Interferometer (MMI) region. An epitaxy process is performed to grow a germanium region in the trench. Electrical connections are made to connect to the p-type region and the n-type region.

There is set forth herein an optoelectrical system comprising: a conductive path for supplying an input voltage to a photonics device, wherein the conductive path comprises a base structure through via extending through a substrate and a photonics structure through via, the photonics structure through via extending through a photonics device dielectric stack. There is set forth herein an optoelectrical system comprising: a second structure fusion bonded to an interposer base dielectric stack of a first structure. There is set forth herein a method comprising: fabricating a second wafer built structure using a second wafer, the second wafer built structure defining a photonics structure and having a photonics device integrated into a photonics device dielectric stack of the second wafer based structure; and wafer scale bonding the second wafer built structure to a first wafer built structure.

A photonic integrated circuit (PIC) includes a semiconductor substrate, one or more passive components, and one or more active components. The one or more passive components are fabricated on the semiconductor substrate, wherein the passive components are fabricated in a III-V type semiconductor layer. The one or more active components are fabricated on top of the one or more passive components, wherein optical signals are communicated between the one or more active components via the one or more passive components.

The invention provides a photonic chip comprising: a silicon substrate, an low refractive index layer above the silicon substrate, and a tapered waveguide above the low refractive index layer, the tapered waveguide having a first height at a first end of the tapered waveguide and a second height at a second end of the tapered waveguide, the second height being greater than the first height, and the tapered waveguide having a bottom surface that is closer to the substrate at the second end than at the first end. The invention further provides a method of manufacturing a photonic chip, the method comprising: providing a wafer comprising a silicon substrate, and an low refractive index layer above the silicon substrate, etching the low refractive index layer to form a tapered trench having a first height at a first end of the tapered trench and a second height at a second end of the tapered trench, the first second height being greater than the second first height, and the tapered trench having a bottom surface that is closer to the substrate at the first second end than at the second first end, and forming a tapered waveguide in the tapered trench.

A semiconductor device for use in an optoelectronic integrated circuit; the device comprising: a group four substrate, a waveguide, and a group III/V multilayer stack; wherein the group III/V multilayer stack comprises a quantum component for producing light for the waveguide; wherein the waveguide comprises a material with a deposition temperature below 550 degrees Celsius and a refractive index of any value between 1.3 and 3.8.

An electro-optical device is fabricated on a semiconductor-on-insulator (SOI) substrate. The electro-optical device comprises a silicon dioxide layer, and an active layer having ferroelectric properties on the silicon dioxide layer. The silicon dioxide layer includes a first silicon dioxide layer of the SOI substrate and a second silicon dioxide layer converted from a silicon layer of the SOI substrate. The active layer includes a buffer layer epitaxially grown on the silicon layer of the SOI substrate and a ferroelectric layer epitaxially grown on the buffer layer. The electro-optical device further comprises one or more additional layers over the active layer, and first and second contacts to the active layer through at least one of the one or more additional layers. Methods of fabricating the electro-optical device are also described herein.

Embodiments of the disclosure provide a waveguide-confining layer, a photonic integrated circuit (PIC) die with embodiments of a waveguide-confining layer, and methods to form the same. The waveguide-confining layer may include an oxide layer over a buried insulator layer, a silicon-based optical confinement structure embedded within or positioned on the oxide layer, and first and second blocking layers over the oxide layer and separated from each other by a horizontal slot. The first and second blocking layers include a metal or an oxide. A gain medium is positioned on the oxide layer and within the horizontal slot between the first and second blocking layers, and has a lower refractive index than each of the first and second blocking layers. The gain medium is vertically aligned with the silicon-based optical confinement structure, and a portion of the oxide layer separates the gain medium from the silicon-based optical confinement structure.