A structure of a silicon photonics device for LIDAR includes a first insulating structure and a second insulating structure disposed above one or more etched silicon structures overlying a substrate member. A metal layer is disposed above the first insulating structure without a prior deposition of a diffusion barrier and adhesion layer. A thin insulating structure is disposed above the second insulating structure. A first configuration of the metal layer, the first insulating structure and the one or more etched silicon structures forms a free-space coupler. A second configuration of the thin insulating structure above the second insulating structure forms an edge coupler.

A semiconductor device is provided. The semiconductor device includes a waveguide over a substrate. The semiconductor device includes a first dielectric structure over the substrate, wherein a portion of the waveguide is in the first dielectric structure. The semiconductor device includes a second dielectric structure under the waveguide, wherein a first sidewall of the second dielectric structure is adjacent a first sidewall of the substrate.

IC chip package with silicon photonic features integrated onto an interposer along with electrical routing redistribution layers. An active side of an IC chip may be electrically coupled to a first side of the interposer through first-level interconnects. The interposer may include a core (e.g., of silicon or glass) with electrical through-vias extending through the core. The redistribution layers may be built up on a second side of the interposer from the through-vias and terminating at interfaces suitable for coupling the package to a host component through second-level interconnects. Silicon photonic features (e.g., of the type in a photonic integrated circuit chip) may be fabricated within a silicon layer of the interposer using high temperature processing, for example of 350° C., or more. The photonic features may be fabricated prior to the fabrication of metallized redistribution layers, which may be subsequently built-up within dielectric material(s) using lower temperature processing.

An integrated optical device fabricated in the back end of line process located within the vertical span of the metal stack and having one or more advantages over a corresponding integrated optical device fabricated in the silicon on insulator layer.

An integrated optical device fabricated in the back end of line process located within the vertical span of the metal stack and having one or more advantages over a corresponding integrated optical device fabricated in the silicon on insulator layer.

An optical element is provided. The optical element includes a substrate; a plurality of metal grids formed on the substrate; an oxide layer formed on the substrate between the plurality of metal grids; and a plurality of organic layers formed on the plurality of metal grids, wherein the width of the organic layer is greater than the width of the metal grid, and there is at least one gap between the organic layer and the oxide layer.

The present disclosure provides a semiconductor device package. The semiconductor device package includes a semiconductor substrate having a first surface and a first optical coupler disposed on the first surface of the semiconductor substrate. The first optical coupler includes a first surface facing away from the first surface of the semiconductor substrate and a first lateral surface connected to the first surface of the first optical coupler. The first surface of the first optical coupler and the first lateral surface of the optical coupler define an angle greater than 90 degrees. A method of manufacturing a semiconductor device package is also disclosed.

Semiconductor device includes light-emitting die and semiconductor package. Light emitting die includes substrate and first conductive pad. Substrate has emission region located at side surface. First conductive pad is located at bottom surface of substrate. Semiconductor package includes semiconductor-on-insulator substrate, interconnection structure, second conductive pad, and through semiconductor via. Semiconductor-on-insulator substrate has linear waveguide formed therein. Interconnection structure is disposed on semiconductor-on-insulator substrate. Edge coupler is embedded within interconnection structure and is connected to linear waveguide. Semiconductor-on-insulator substrate and interconnection structure include recess in which light-emitting die is disposed. Edge coupler is located close to sidewall of recess. Second conductive pad is located at bottom of recess. Through semiconductor via extends across semiconductor-on-insulator substrate to contact second conductive pad. First conductive pad is connected to through semiconductor via. Emission region directly faces sidewall of recess where edge coupler is located.

The wavelength response of an arrayed waveguide grating can be tuned, in accordance with various embodiments, using a beam sweeper including one or more heaters to shift a lateral position of light focused by the beam sweeper at an interface of the beam sweeper with an input free propagation region of the arrayed waveguide grating.

The wavelength response of an arrayed waveguide grating can be tuned, in accordance with various embodiments, using a beam sweeper including one or more heaters to shift a lateral position of light focused by the beam sweeper at an interface of the beam sweeper with an input free propagation region of the arrayed waveguide grating.