A chip-scale transceiver includes an interposer having microspring electrical contacts disposed on the interposer substrate. At least one electronic chip and at least one optoelectronic chip are electrically coupled to the interposer through the microsprings. The electronic chip includes at least one of an amplifier array and a laser driver array. First electrical contact pads arranged to make electrical contact with the first microsprings of the interposer. The optoelectronic chip includes at least one of a laser array and a photodetector array. Second electrical contact pads arranged to make electrical contact with the second microsprings of the interposer are disposed on the optoelectronic chip substrate. The transceiver has an area less than or equal to 0.17 mm.sup.2 per Gbps.

An optical receptacle includes an optical receptacle main body and a cylindrical fixing member. The optical receptacle main body includes a first optical surface, a second optical surface, and an annular groove disposed to surround a first central axis of the first optical surface or disposed to surround a second central axis of the second optical surface. The fixing member is configured with a material with a smaller linear expansion coefficient than that of the optical receptacle main body, and is fit to the groove so as to be in contact with at least a part of an inner surface of the groove.

A connector assembly includes a connector, an optical waveguide and a circuit board having a through-hole and a transmitter/receiver configured to transmit and/or receive light signals. The connector is interlockingly and releasably connected to the circuit board via a fastening element which is passed through the through-hole and connected to the circuit board. The connector has a receiving chamber which at least partially borders the transmitter/receiver. A lens unit is disposed in the receiving chamber and light-conductively connects the transmitter/receiver to the optical waveguide. A locking element is movably disposed on the connector. The locking element is disposed at least partially within the receiving chamber and secures the lens unit in the receiving chamber. The locking element is movable into a final latched position in which the locking element extends at least partially into the through-hole and blocks release of the fastening element from the circuit board.

Systems and methods described herein relate to the manufacture of optical elements and optical systems. An example method includes providing a first substrate that has a plurality of light-emitter devices disposed on a first surface. The method includes providing a second substrate that has a mounting surface defining a reference plane. The method includes forming a structure and an optical spacer on the mounting surface of the second substrate. The method additionally includes coupling the first and second substrates together such that the first surface of the first substrate faces the mounting surface of the second substrate at an angle with respect to the reference plane.

Various embodiments provide a method for fabricating a couplable electro-optical device. In an example embodiment, the method includes fabricating at least one raw electro-optical device on a substrate; applying lens material to a working stamp; aligning the substrate and the working stamp; pressing the substrate onto the lens material until the distance between the substrate and the working stamp is a predetermined distance; and curing the lens material to form an integrated lens secured to the at least one electro-optical device on the substrate. An anti-reflective coating layer may be optionally applied on top of the molded lens. The couplable electro-optical device may be incorporated into a receiver, transmitter, and/or transceiver using passive alignment to align the couplable electro-optical device to an optical fiber.

An interconnect package integrates a photonic die, an electronic die, and a switch ASIC into one package. At least some of the components in the electronic die, such as, for example, the serializer/deserializer circuits, transceivers, clocking circuitry, and/or control circuitry are integrated into the switch ASIC to produce an integrated switch ASIC. The photonic die is attached and electrically connected to the integrated switch ASIC.

An optoelectronic device includes a photonic component. The photonic component includes an active side, a second side different from the active side, and an optical channel extending from the active side to the second side of the photonic component. The optical channel includes a non-gaseous material configured to transmit light.

Semiconductor device includes light-emitting die and semiconductor package. Light emitting die includes substrate and first conductive pad. Substrate has emission region located at side surface. First conductive pad is located at bottom surface of substrate. Semiconductor package includes semiconductor-on-insulator substrate, interconnection structure, second conductive pad, and through semiconductor via. Semiconductor-on-insulator substrate has linear waveguide formed therein. Interconnection structure is disposed on semiconductor-on-insulator substrate. Edge coupler is embedded within interconnection structure and is connected to linear waveguide. Semiconductor-on-insulator substrate and interconnection structure include recess in which light-emitting die is disposed. Edge coupler is located close to sidewall of recess. Second conductive pad is located at bottom of recess. Through semiconductor via extends across semiconductor-on-insulator substrate to contact second conductive pad. First conductive pad is connected to through semiconductor via. Emission region directly faces sidewall of recess where edge coupler is located.

Microstructures of micro and/or nano holes on one or more surfaces enhance photodetector optical sensitivity. Arrangements such as a CMOS Image Sensor (CIS) as an imaging LIDAR using a high speed photodetector array wafer of Si, Ge, a Ge alloy on SI and/or Si on Ge on Si, and a wafer of CMOS Logic Processor (CLP) ib Si fi signal amplification, processing and/or transmission can be stacked for electrical interaction. The wafers can be fabricated separately and then stacked or can be regions of the same monolithic chip. The image can be a time-of-flight image. Bayer arrays can be enhanced with microstructure holes. Pixels can be photodiodes, avalanche photodiodes, single photon avalanche photodiodes and phototransistors on the same array and can be Ge or Si pixels. The array can be of high speed photodetectors with data rates of 56 Gigabits per second, Gbps, or more per photodetector.

Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.