An optical element mounting module includes a wiring board including an upper surface and a terminal, an optical waveguide on the upper surface and the terminal, and an optical element on the optical waveguide, including a light emitting/receiving portion having a convex shape and an electrode. The optical waveguide includes a lower cladding layer, a core on the lower cladding layer, an upper cladding layer, a cavity between the upper surface of the upper cladding layer to the lower cladding layer for dividing the core, a through hole passing through the upper to the lower cladding layer to the terminal, and a conductive material in the through hole and connected to the electrode and the terminal. The light emitting/receiving portion includes a first part on the upper cladding layer and a second part between the upper surface of the upper cladding layer and the lower surface of the optical element.

Apparatus and methods of manufacture are disclosed. In one example the apparatus includes a first substrate that has a first surface, a first optical waveguide that is at or near the first surface of the first substrate, a second substrate that has a second surface. The second substrate is coupled to the first substrate at an interface. The apparatus also has a photonic integrated circuit (PIC) with a portion at or near the second surface. The PIC is in alignment with and optically coupled to the first optical waveguide across the interface.

Embodiments described herein may be related to apparatuses, processes, and techniques related to multilevel dies, in particular to photonics integrated circuit dies with a thick portion and a thin portion, where the thick portion is placed within a cavity in a substrate and the thin portion serves as an overhang to physically couple with the substrate, to reduce a distance between electrical contacts on the thin portion of the die and electrical contacts on the substrate. Other embodiments may be described and/or claimed.

Embodiments described herein may be related to apparatuses, processes, and techniques related to creating deep cavities within a substrate or at an edge of the substrate, by etching a cavity in the substrate to a first copper stop layer, removing the first copper stop layer, and then etching deeper into the cavity to a second copper stop layer. In embodiments this process may be repeated until the desired cavity depth is reached. Other embodiments may be described and/or claimed.

Embodiments described herein may be related to apparatuses, processes, and techniques related to thermally and/or electrically coupling a thermal die to the surface of a photonic integrated circuit (PIC) within an open cavity in a substrate, where the thermal die is proximate to a laser on the PIC. Other embodiments may be described and/or claimed.

A system includes a plurality of wafer-scale modules and a plurality of optical fibers. Each wafer-scale module includes an optical backplane and one or more die stacks on the optical backplane. The optical backplane includes a substrate and at least one optical waveguide layer configured to transport and/or manipulate photonic quantum systems (e.g., photons, qubits, qudits, large entangled states, etc.). Each die stack of the one or more die stacks includes a photonic integrated circuit (PIC) die optically coupled to the at least one optical waveguide layer of the optical backplane. The plurality of optical fibers is coupled to the optical backplanes of the plurality of wafer-scale modules to provide inter-module and/or intra-module interconnects for the photonic quantum systems.

Embodiments disclosed herein include electronic packages with a core that includes an optical waveguide and methods of forming such electronic packages. In an embodiment, a package substrate comprises a core, and a photonics die embedded in the core. In an embodiment, the electronic package further comprises an optical waveguide embedded in the core. In an embodiment, the optical waveguide optically couples the photonics die to an edge of the core.

An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.

An electronic assembly, such as an integrated circuit package, may be formed comprising a package substrate and a photonic integrated circuit device attached thereto, wherein the package substrate includes a heat dissipation structure disposed therein. A back surface of the photonic integrated circuit device may thermally coupled to the heat dissipation structure within the package substrate for the removal of heat from the photonic integrated circuit device, which allows for access to an active surface of the photonic integrated circuit device for the attachment of fiber optic cables and eliminates the need for a heat dissipation device to be thermally attached to the active surface of the photonic integrated circuit device.

Disclosed herein are microelectronics packages and methods for manufacturing the same. The microelectronics packages may include a photonic integrated circuit (PIC), an electrical integrated circuit (EIC), and an interconnect. The interconnect may connect the EIC to the PIC. The interconnect may include a plurality of paths between the EIC and the PIC and the individual paths of the plurality of paths are less than 100 micrometers long.