Patent classifications
G02F1/01708
High-Speed Wavelength-Scale Spatial Light Modulators with Two-Dimensional Tunable Microcavity Arrays
A reflective spatial light modulator (SLM) made of an electro-optic material, such as barium titanate, in a one-sided Fabry-Perot resonator can provide phase and/or amplitude modulation with fine spatial resolution at speeds over a Gigahertz. The light is confined laterally within the electro-optic material/resonator layer stack with microlenses, index perturbations, or by patterning the layer stack into a two-dimensional (2D) array of vertically oriented micropillars. Alternatively, a photonic crystal guided mode resonator can provide vertical and lateral confinement of the resonant mode. In phase-only modulation mode, each pixel in the SLM can produce a phase shift under a bias voltage below 10 V, while maintaining nearly constant reflection amplitude. The methodology for designing this SLM could also be used to design other SLMs (for example, amplitude-only SLMs). This high-speed SLM can be used in a wide range of new applications, from fully tunable metasurfaces to optical computing accelerators, high-speed interconnects, true 2D phased array beam steering, beam forming, or quantum computing with cold atom arrays.
Photonic and electric devices on a common layer
Photonic devices having Al.sub.1-xSc.sub.xN and Al.sub.yGa.sub.1-yN materials, where Al is Aluminum, Sc is Scandium, Ga is Gallium, and N is Nitrogen and where 0<x0.45 and 0y1.
Semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice
A semiconductor device may include a substrate having waveguides thereon, and a superlattice overlying the substrate and waveguides. The superlattice may include stacked groups of layers, with each group of layers comprising a stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include an active device layer on the superlattice including at least one active semiconductor device.
Display screen, splicing display screen and display device
A display screen includes: a display panel with a display region and a non-display region, wherein the display region includes an intermediate display region and a peripheral display region surrounding the intermediate display region; an image expansion structure disposed in the peripheral display region, wherein the image expansion structure is configured to expand an image displayed by the peripheral display region of the display panel to the non-display region to cover the non-display region.
ON-CHIP HIGH CAPACITANCE TERMINATION FOR TRANSMITTERS
A modulator and a capacitor are integrated on a semiconductor substrate for modulating a laser beam. Integrating the capacitor on the substrate reduces parasitic inductance for high-speed optical communication.
Folded waveguide phase shifters
In an embodiment, a phase shifter includes: a light input end; a light output end; a p-type semiconductor material, and an n-type semiconductor material contacting the p-type semiconductor material along a boundary area, wherein the boundary area is greater than a length from the light input end to the light output end multiplied by a core width of the phase shifter.
OPTOELECTRONIC DEVICE AND ARRAY THEREOF
An optoelectronic device and an array comprising a plurality of the same. The device(s) comprising: an optically active region with an electrode arrangement for applying an electric field across the optically active region; a first curved waveguide, arranged to guide light into the optically active region; and a second curved waveguide, arranged to guide light out of the optically active region; wherein the first curved waveguide and the second curved waveguide are formed of a material having a different band-gap from a band-gap of the optically active region, and wherein the overall guided path formed by the first curved waveguide, the optically active region and the second curved waveguide is U-shaped.
OPTICAL INTEGRATED ELEMENT AND OPTICAL MODULE
An optical integrated element includes: a substrate; a first waveguide region in which a lower cladding layer, a first core layer, and an upper cladding layer are sequentially laminated in this order on the substrate; and an active region in which the lower cladding layer, a second core layer, a quantum well layer that amplifies light when a current is injected, and the upper cladding layer are sequentially laminated on the substrate. Further, the second core layer and the quantum well layer are close to each other within a range of a mode field of light guided in the second core layer, and the first core layer is butt-jointed to the second core layer and the quantum well layer.
ELECTRO-OPTICALLY ACTIVE DEVICE
A silicon based electro-optically active device and method of producing the same. The silicon based electro-optically active device comprising: a silicon-on-insulator (SOI) waveguide; an electro-optically active waveguide including an electro-optically active stack within a cavity of the SOI waveguide; and a lined channel between the electro-optically active stack and the SOI waveguide, the lined channel comprising a liner; wherein the lined channel is filled with a filling material with a refractive index similar to that of a material forming a sidewall of the cavity, to thereby form a bridge-waveguide in the channel between the SOI waveguide and the electro-optically active stack.
INTEGRATED OPTOELECTRONIC DEVICE WITH HEATER
Disclosed are structures as well as methods of manufacture and operation of integrated optoelectronic devices that facilitate directly heating the diode or waveguide structures to regulate a temperature of the device while allowing electrical contacts to be placed close to the device to reduce the electrical resistance. Embodiments include, in particular, heterogeneous electro-absorption modulators that include a compound-semiconductor diode structure placed above a waveguide formed in the device layer of an SOI substrate.