A semiconductor integrated circuit design method and apparatus, and relates to the technical field of semiconductors are provided. The semiconductor integrated circuit design method includes: determining, based on an original layout, an original length of an end of a gate structure extending out of an active region in which the gate structure is located; redetermining, based on a preset rule and the original length, a correction length of the end of the gate structure extending out of the active region in which the gate structure is located; and integrating the original layout and the correction lengths, and forming an updated layout.

Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns. The plurality of intended circuit layout patterns is ranked based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both. At least a portion of ranking information is outputted to facilitate influence or control over the semiconductor fabrication process.

A method of making a mask includes computing a mask volume correction matrix for a given mask layout to be used to perform a lithography process. The mask volume correction matrix represents a diffraction field for a predetermined thickness of a material of the mask. A simulated mask pattern is computed by applying the mask volume correction matrix to the given mask layout. The simulated mask pattern is provided to a mask making tool.

According to one embodiment, a method for displaying an index value in generation of a mask pattern verification model includes: calculating a first index value using a plurality of images; estimating a model on the basis of the first index value and pattern information; calculating a second index value using the model; and displaying at least one of the first index value and the second index value.

A method for source mask optimization or mask only optimization used to image a pattern onto a substrate. The method includes determining a non-uniform illumination intensity profile for illumination; and determining one or more adjustments for the pattern based on the non-uniform illumination intensity profile until a determination that features patterned onto a substrate substantially match a target design. The non-uniform illumination intensity profile may be determined based on an illumination optical system and projection optics of a lithographic apparatus. In some embodiments, the lithographic apparatus includes a slit, and the non-uniform illumination profile is a through slit non-uniform illumination intensity profile. Determining the one or more adjustments for the pattern may include performing optical proximity correction, for example.

A method for correcting mask patterns includes providing a target layout, including a plurality of main patterns; dividing the target layout into a plurality of first regions along a first direction; acquiring position information of each first region of the plurality of first regions; acquiring a first model of each first region according to the position information of the first region; acquiring pattern parameters of auxiliary patterns around each main pattern of the first region; and arranging, around each main pattern, the auxiliary patterns of the main pattern according to the pattern parameters of the auxiliary patterns.

A method for manufacturing a semiconductor device, includes receiving a first layout including patterns for the manufacturing of the semiconductor device, generating a second layout by performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout, generating a third layout by performing optical proximity correction (OPC) on the second layout, and performing a multiple patterning process based on the third layout. The multiple patterning process includes patterning first-type patterns, and patterning second-type patterns. The machine learning-based process proximity correction is performed based on features of the first-type patterns and features of the second-type patterns.

A deep trench layout implementation for a semiconductor device is provided. The semiconductor device includes an isolation film with a shallow depth, an active area, and a gate electrode formed in a substrate; a deep trench isolation surrounding the gate electrode and having one or more trench corners; and a gap-fill insulating film formed inside the deep trench isolation. The one or more trench corners is formed in a slanted shape from a top view.

A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.

An exposure system according to an aspect of the present disclosure includes a laser apparatus emitting a pulse laser beam, an illumination optical system guiding the pulse laser beam to a reticle, a reticle stage moving the reticle, and a processor controlling emission of the pulse laser beam and movement of the reticle. The exposure system performs scanning exposure of a semiconductor substrate by irradiating the reticle with the pulse laser beam. The reticle has first and second regions. The processor instructs the laser apparatus about, based on proximity effect characteristics corresponding to the first and second regions, a value of a control parameter of the pulse laser beam corresponding to each region so that the laser apparatus emits the pulse laser beam with which a difference of the proximity effect characteristic of each region from a reference proximity effect characteristic is in an allowable range.