A method for determining process window limiting patterns based on aberration sensitivity associated with a patterning apparatus. The method includes obtaining (i) a first set of kernels and a second set of kernels associated with an aberration wavefront of the patterning apparatus and (ii) a design layout to be printed on a substrate via the patterning apparatus; and determining, via a process simulation using the design layout, the first set of kernels, and the second set of kernels, an aberration sensitivity map associated with the aberration wavefront, the aberration sensitivity map indicating how sensitive one or more portions of the design layout are to an individual aberrations and an interaction between different aberrations; determining, based on the aberration sensitivity map, the process window limiting pattern associated with the design layout having relatively high sensitivity compared to other portions of the design layout.

Methods of generating a characteristic pattern for a patterning process and training a machine learning model. A method of training a machine learning model configured to generate a characteristic pattern for a mask pattern includes obtaining (i) a reference characteristic pattern that meets a satisfactory threshold related to manufacturing of the mask pattern, and (ii) a continuous transmission mask (CTM) for use in generating the mask pattern; and training, based on the reference characteristic pattern and the CTM, the machine learning model such that a first metric between the characteristic pattern and the CTM, and a second metric between the characteristic pattern and the reference characteristic pattern is reduced.

Methods of fabricating lithographic masks include performing mask process correction (MPC) on a mask tape out (MTO) design layout. Performing MPC may include identifying a plurality of unit cells (each being iterated in the MTO design layout and including a plurality of curve patterns), and performing model-based MPC on at least one of the plurality of unit cells. These methods may further include performing electron beam exposure based on the MTO design layout on which the MPC is performed. The performing model-based MPC on at least one of the plurality of unit cells may be based on at least one of an aspect ratio, sizes, curvatures of curved edges, density, and a duty of the plurality of curve patterns.

A method of manufacturing a semiconductor chip includes designing a layout for a semiconductor chip, performing an optical proximity correction (OPC) on the layout, manufacturing a mask after performing the OPC, and manufacturing the semiconductor chip using the mask, wherein a plurality of OPC shapes corresponding to a rectangular pattern of the mask are included in the mask and at least one of the plurality of OPC shapes includes a multi-edge corner rounding OPC shape.

An optical proximity correction method includes extracting first patterns from a pattern mask, performing lithography on at least a part of the first patterns to form first-first patterns, forming the first-first patterns at positions where the first patterns are formed, and performing correction on the pattern mask on which the first-first patterns are formed.

A method of generating a mask used in fabrication of a semiconductor device includes, in part, selecting a source candidate, generating a process simulation model that includes a stochastic variance band model in response to the selected source candidate, performing a first optical proximity correction (OPC) on the data associated with the mask in response to the process simulation model, assessing one or more lithographic evaluation metrics in response to the OPC mask data, computing a cost in response to the assessed one or more lithographic evaluation metrics, and determining whether the computed cost satisfies a threshold condition. In response to the determination that the computed cost does not satisfy the threshold condition, a different source candidate may be selected.

A method of designing a semiconductor device includes creating a library for test patterns on a frame and an on purpose violation layout on a main chip of a layout, and then creating filter marks according to the library. An OPC (optical proximity correction) is run using the layout, and an OPC verifying is performed for obtaining a pattern with hot spots to determine whether the hot spots are within the frame and the filter marks. When the hot spots are within the frame and the filter marks, a mask can be made. When the hot spots are outside the frame and the filter marks, it is necessary to check whether the hot spots need to be repaired. When the hot spots are within the frame and outside the filter marks, the hot spots are added into the library as data of the on purpose violation layout.

A system and a method of optimizing an optical proximity correction (OPC) model for a mask pattern of a photo mask is disclosed. A machine learning (ML) based model builder includes an OPC model, measurement data and a random term generator. Random terms are generated in a M-dimensional space by the random term generator. The ML based model builder classifies the random terms to clusters by applying a classifying rule. A representative subset of the random terms is determined among the classified clusters, and the representative subset is added to the OPC model.

In a method of manufacturing a lithographic mask of an integrated circuit for semiconductor device manufacturing an optical proximity correction (OPC) process to a layout pattern of the integrated circuit is performed to produce a corrected layout pattern. An inverse lithographic technology (ILT) process to the corrected layout pattern is also performed to enhance the corrected layout pattern to produce an OPC-ILT-enhanced layout pattern of the lithographic mask. A first contour image associated with the OPC-ILT-enhanced layout pattern is generated when the OPC-ILT-enhanced layout pattern of the lithographic mask is projected on a wafer. The features of the generated first contour image are extracted. And a second contour image of a developed photo resist pattern on the wafer associated with the OPC-ILT-enhanced layout pattern as an output of a deep neural network is generated.

Disclosed are a method of forming an optical proximity correction (OPC) model and/or a method of fabricating a semiconductor device using the same. The method of forming the OPC model may include obtaining a scanning electron microscope (SEM) image, which is an average image of a plurality of images taken using one or more scanning electron microscopes, and a graphic data system (GDS) image, which is obtained by imaging a designed layout, aligning the SEM image and the GDS image, performing an image filtering process on the SEM image, extracting a contour from the SEM image, and verifying the contour. The verifying of the contour may be performed using a genetic algorithm. Variables in the genetic algorithm may include first parameters related to the image alignment process, second parameters related to the image filtering process, and third parameters related to a critical dimension (CD) measurement process.