A method of generating chip-specific identification code marks on semiconductor chips includes patterning a resist layer over a semiconductor wafer by laser direct image exposure, the patterning including writing chip-specific identification codes into the resist layer over chip areas of the semiconductor wafer. The patterned resist layer is then developed.

The invention concerns a method of manufacturing an assembly of electronic components (3) on the front surface of a semiconductor wafer (1) comprising a plurality of field areas (4), each area (4) comprising at least one field (2) and each field (2) comprising at least one electronic component (3). The method comprises a plurality of photolithography steps to form a stack of layers forming each electronic component (3), each photolithography step comprises the application of a mask successively on each field (2) in photolithography equipment. One of the masks further comprises an identification pattern, said mask being called identification mask. At the photolithography step associated with the identification mask, as least one photolithographic parameter of the photolithography equipment is different for each field area (4), to expose the identification pattern differently in each field area (4).

A system includes a first mask, a second mask and a mask container. The first mask includes a first identification code and a second identification code. The second mask includes a third identification code and a fourth identification code. The mask container is configured to store the first mask and the second mask. The first identification code is different from the third identification code. In response to a pattern, for performing a photolithography process, on the first mask, that is different from a pattern on the second mask, the second identification code is different from the fourth identification code. In response to the pattern on the first mask being the same as the pattern on the second mask, the second identification code is the same as the fourth identification code.

A method for verifying semiconductor wafers includes receiving a semiconductor wafer including a plurality of layers. A first set of measurement data is obtained for at least one layer of the plurality of layers, where the first set of measurement data includes at least one previously recorded thickness measurement for one or more portions of the at least one layer. The first set of measurement data is compared to a second set of measurement data for the at least one layer. The second set of measurement data includes at least one new thickness measurement for the one or more portions of the at least one layer. The semiconductor wafer is determined to be an authentic wafer based on the second set of measurement data corresponding to the first set of measurement data, otherwise the semiconductor is determined to not be an authentic wafer.

The present application provides a method, an apparatus, and a system for forming code. The method includes while a substrate is transferred to an exposure machine, adjusting the substrate to align with an exposure alignment mark on the substrate with the exposure machine; forming a code formation area on the adjusted substrate by controlling the exposure machine; while the substrate formed with the code formation area is transferred to a code formation machine, adjusting the substrate to align the exposure alignment mark on the substrate with the code formation machine; and forming an identification code in the code formation area on the adjusted substrate by controlling the code formation machine.

A system includes a plurality of masks and a scanner device. A pattern of a semiconductor device is defined by each of the plurality of masks in a photolithography process. A first mask of the plurality of masks includes a first identification code configured to distinguish the first mask from remaining masks of the plurality of masks. The scanner device is configured to read the first identification code to select the first mask from the plurality of mask, in order to form the pattern of the semiconductor device on a substrate according to the first mask.

The present application provides a method, an apparatus, and a system for forming code. The method includes while a substrate is transferred to an exposure machine, adjusting the substrate to align with an exposure alignment mark on the substrate with the exposure machine; forming a code formation area on the adjusted substrate by controlling the exposure machine; while the substrate formed with the code formation area is transferred to a code formation machine, adjusting the substrate to align the exposure alignment mark on the substrate with the code formation machine; and forming an identification code in the code formation area on the adjusted substrate by controlling the code formation machine.

Cantilever-Free Scanning Probe Lithography (CF-SPL) techniques are used to enable generation of 1-, 2-, 3-, and 4-D information containing patterns in a mask-free manner that, in turn, enables instantaneous change of pattern design.

A method of topography determination, the method including: obtaining a first focus value derived from a computational lithography model modeling patterning of an unpatterned substrate or derived from measurements of a patterned layer on an unpatterned substrate; obtaining a second focus value derived from measurement of a substrate having a topography; and determining a value of the topography from the first and second focus values.

A method for verifying semiconductor wafers includes receiving a semiconductor wafer including a plurality of layers. A first set of measurement data is obtained for at least one layer of the plurality of layers, where the first set of measurement data includes at least one previously recorded thickness measurement for one or more portions of the at least one layer. The first set of measurement data is compared to a second set of measurement data for the at least one layer. The second set of measurement data includes at least one new thickness measurement for the one or more portions of the at least one layer. The semiconductor wafer is determined to be an authentic wafer based on the second set of measurement data corresponding to the first set of measurement data, otherwise the semiconductor is determined to not be an authentic wafer.