Methods and systems for performing simultaneous spectroscopic measurements of semiconductor structures over a broad range of angles of incidence (AOI), azimuth angles, or both, are presented herein. Spectra including two or more sub-ranges of angles of incidence, azimuth angles, or both, are simultaneously measured over different sensor areas at high throughput. Collected light is linearly dispersed across different photosensitive areas of one or more detectors according to wavelength for each subrange of AOIs, azimuth angles, or both. Each different photosensitive area is arranged on the one or more detectors to perform a separate spectroscopic measurement for each different range of AOIs, azimuth angles, or both. In this manner, a broad range of AOIs, azimuth angles, or both, are detected with high signal to noise ratio, simultaneously. This approach enables high throughput measurements of high aspect ratio structures with high throughput, precision, and accuracy.

Multi-layered targets, design files and design and production methods thereof are provided. The multi-layered targets comprise process layers arranged to have parallel segmentation features at specified regions, and target layer comprising target elements which are perpendicular to the parallel segmentation features of the process layers at the specified regions.

A process of selecting a measurement location, the process including: obtaining pattern data describing a pattern to be applied to substrates in a patterning process; obtaining a process characteristic measured during or following processing of a substrate, the process characteristic characterizing the processing of the substrate; determining a simulated result of the patterning process based on the pattern data and the process characteristic; and selecting a measurement location for the substrate based on the simulated result.

A method for selecting an optimal set of locations for a measurement or feature on a substrate, the method includes: defining a first candidate solution of locations, defining a second candidate solution with locations based on modification of a coordinate in a solution domain of the first candidate solution, and selecting the first and/or second candidate solution as the optimal solution according to a constraint associated with the substrate.

A controller is configured to perform at least a first characterization process prior to at least one discrete backside film deposition process on a semiconductor wafer; perform at least an additional characterization process following the at least one discrete backside film deposition process; determine at least one of a film force or one or more in-plane displacements for at least one discrete backside film deposited on the semiconductor wafer via the at least one discrete backside film deposition process based on the at least the first characterization process and the at least the additional characterization process; and provide at least one of the film force or the one or more in-plane displacements to at least one process tool via at least one of a feed forward loop or a feedback loop to improve performance of one or more fabrication processes.

An optical apparatus and a lithographic apparatus including the optical apparatus. The optical apparatus includes a substrate having an aperture for passing light; a transmissive optical element covering the aperture of the substrate; and an optical contact bond between the substrate and transmissive optical element, the optical contact bond being spaced from the aperture a sufficient distance such that stress forces in the transmissive optical element from the optical contact bond to the aperture are below an acceptable stress threshold. The optical contact bond geometry herein, for example, minimizes a contact area and provides a quasi-kinematic (near-exactly constrained) interface between the substrate and the optical element.

A method and system are presented for use in measuring one or more characteristics of patterned structures. The method comprises: performing measurements on a patterned structure by illuminating the structure with exciting light to cause Raman scattering of one or more excited regions of the pattern structure, while applying a controlled change of at least temperature condition of the patterned structure, and detecting the Raman scattering, and generating corresponding measured data indicative of a temperature dependence of the detected Raman scattering; and analyzing the measured data and generating data indicative of spatial profile of one or more properties of the patterned structure.

A method for inspecting a group of dies of a wafer, wherein the wafer comprises a group of wafer segments, wherein each wafer segment comprises a die of the group of dies, a molded material that surrounds the die and redistribution layer (RDL) conductors that are coupled to the die and are positioned above the die and the molded material, wherein the method includes the steps of: receiving design information about the RDL conductors of each wafer segment of the group of wafer segments; obtaining, during a setup process, first images of the group of wafer segments; wherein the obtaining of the first images comprises illuminating the group of wafer segments with radiation and detecting radiation scattered or reflected from the group of wafer segments as a result of the illuminating; generating reference information based on the design information about the RDL conductors of one or more wafer segments of the group of wafer segments and at least one first image of the one or more first images; acquiring, during an inspection process, a second image of each wafer segment of the group of wafer segments; and evaluating each wafer segment of the group of wafer segments based on the second image of the wafer segment and the reference information of the wafer segment.

In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.

A method and associated apparatuses for optimizing a sampling scheme which defines sampling locations on a bonded substrate, having undergone a wafer to wafer bonding process. The method includes determining a sampling scheme for a metrology process and optimizing the sampling scheme with respect to a singularity defined by a large overlay error and/or grid deformation at a central location on the bonded substrate to obtain a modified sampling scheme.