G03F7/70616

ILLUMINATION APPARATUS AND ASSOCIATED METROLOGY AND LITHOGRAPHIC APPARATUSES

Disclosed is an illumination arrangement for spectrally shaping a broadband illumination beam to obtain a spectrally shaped illumination beam. The illumination arrangement comprises a beam dispersing element for dispersing the broadband illumination beam and a spatial light modulator for spatially modulating the broadband illumination beam subsequent to being dispersed. The illumination arrangement further comprises at least one of a beam expanding element for expanding said broadband illumination beam in at least one direction, located between an input of the illumination arrangement and the spatial light modulator; and a lens array, each lens of which for directing a respective wavelength band of the broadband illumination beam subsequent to being dispersed onto a respective region of the spatial light modulator.

MARK TO BE PROJECTED ON AN OBJECT DURING A LITHOGRAHPIC PROCESS AND METHOD FOR DESIGNING A MARK
20230229093 · 2023-07-20 · ·

The first layer mark and the second layer mark are adapted to be projected onto each other during the lithographic process. The first layer components and the second layer components are adapted to be arranged in a plurality of different overlay configurations, each overlay configuration comprising a number of the plurality of the first layer components and a number of the plurality of the second layer components, and each overlay configuration having a different overlay distance at which each first layer component is arranged in a first direction of an associated second layer component of the second layer components. The method comprises determining an overlay step which represents a difference between the different overlay distances of the plurality of overlay configurations, determining a largest overlay distance, determining the number of first layer components and/or the number of associated second layer components in each overlay configuration.

System and method for inspecting a wafer

A computer-implemented defect prediction method for a device manufacturing process involving processing a pattern onto a substrate. Non-correctable error is used to help predict locations where defects are likely to be present, allowing improvements in metrology throughput. In an embodiment, non-correctable error information relates to imaging error due to limitations on, for example, the lens hardware, imaging slit size, and/or other physical characteristics of the lithography system. In an embodiment, non-correctable error information relates to imaging error induced by lens heating effects.

Recipe selection based on inter-recipe consistency

A method including: determining recipe consistencies between one substrate measurement recipe of a plurality of substrate measurement recipes and each other substrate measurement recipe of the plurality of substrate measurement recipes; calculating a function of the recipe consistencies; eliminating the one substrate measurement recipe from the plurality of substrate measurement recipes if the function meets a criterion; and reiterating the determining, calculating and eliminating until a termination condition is met. Also disclosed herein is a substrate measurement apparatus, including a storage configured to store a plurality of substrate measurement recipes, and a processor configured to select one or more substrate measurement recipes from the plurality of substrate measurement recipes based on recipe consistencies among the plurality of substrate measurement recipes.

Reflectivity and transmittance measuring device of EUV mask and EUV pellicle
11561467 · 2023-01-24 · ·

A reflectivity and transmittance measuring device includes: an EUV light source for outputting EUV light with a wavelength ranging from 5 nm to 15 nm; a multilayer reflection zone plate having an EUV reflection multilayer film, which is a planar substrate, and a zone plate pattern; and an EUV lighting unit for creating EUV illumination light by obtaining 1.sup.st diffraction light reflected after radiating EUV light output from the EUV light source to the multilayer reflection zone plate.

METROLOGY METHOD AND ASSOCIATED METROLOGY AND LITHOGRAPHIC APPARATUSES

A metrology method relating to measurement of a structure on a substrate, the structure being subject to one or more asymmetric deviation. The method includes obtaining at least one intensity asymmetry value relating to the one or more asymmetric deviations, wherein the at least one intensity asymmetry value includes a metric related to a difference or imbalance between the respective intensities or amplitudes of at least two diffraction orders of radiation diffracted by the structure; determining at least one phase offset value corresponding to the one or more asymmetric deviations based on the at least one intensity asymmetry value; and determining one or more measurement corrections for the one or more asymmetric deviations from the at least one phase offset value.

DETECTING OUTLIERS AND ANOMALIES FOR OCD METROLOGY MACHINE LEARNING

A system and methods for OCD metrology are provided including receiving training data for training an OCD machine learning (ML) model, including multiple pairs of corresponding sets of scatterometric data and reference parameters. For each of the pairs, one or more corresponding outlier metrics are by calculated and corresponding outlier thresholds are applied whether a given pair is an outlier pair. The OCD MIL model is then trained with the training data less the outlier pairs.

ASSEMBLY FOR COLLIMATING BROADBAND RADIATION

An assembly for collimating broadband radiation, the assembly including: a convex refractive singlet lens having a first spherical surface for coupling the broadband radiation into the lens and a second spherical surface for coupling the broadband radiation out of the lens, wherein the first and second spherical surfaces have a common center; and a mount for holding the convex refractive singlet lens at a plurality of contact points having a centroid coinciding with the common center.

Methods and apparatus for monitoring a manufacturing process, inspection apparatus, lithographic system, device manufacturing method

Multilayered product structures are formed on substrates by a combination of patterning steps, physical processing steps and chemical processing steps. An inspection apparatus illuminates a plurality of target structures and captures pupil images representing the angular distribution of radiation scattered by each target structure. The target structures have the same design but are formed at different locations on a substrate and/or on different substrates. Based on a comparison of the images the inspection apparatus infers the presence of process-induced stack variations between the different locations. In one application, the inspection apparatus separately measures overlay performance of the manufacturing process based on dark-field images, combined with previously determined calibration information. The calibration is adjusted for each target, depending on the stack variations inferred from the pupil images.

Die yield assessment based on pattern-failure rate simulation

This application discloses a computing system to identify structures of an integrated circuit capable of being fabricated utilizing a lithographic mask described by mask layout data and to generate process windows for the identified structures based, at least in part, on the mask layout data and a failure definition for the identified structures. The computing system utilizes process windows for the identified structures to determine failure rates for the identified structures based on a distribution of the manufacturing parameters. The computing system determines frequency of occurrences for the identified structures from the mask layout data and generates a die yield metric for the integrated circuit by aggregating the failure rates for the identified structures based on the frequency of occurrences for the identified structures in the integrated circuit. These increases in yield of the integrated circuit allow manufacturers to produce more units per fixed processing cost of the wafer.