G03F7/70866

Cleaning method, method for forming semiconductor structure and system thereof

A method for cleaning a reflective photomask is provided. The method includes: disposing the reflective photomask in a chamber; providing hydrogen radicals to the chamber; and exposing the reflective photomask to the hydrogen radicals. A method of manufacturing a semiconductor structure and system for forming a semiconductor structure are also provided.

METHOD AND APPARATUS FOR MITIGATING CONTAMINATION

An extreme ultra violet (EUV) lithography method includes receiving an EUV light by a scanner from an EUV light source, the EUV light passing through an intermediate focus disposed in the scanner and at a junction of the EUV light source and the scanner; directing the EUV light by the scanner to a reticle in the scanner; and deflecting nanoparticles from the EUV light source away from the reticle by generating a gas flow using a gas jet disposed entirely in the scanner and proximate to an interface of the scanner and the intermediate focus such that the gas jet does not block the EUV light.

Mask cleaning

A lithography system includes a first load lock chamber configured to receive a mask, a cleaning module configured to clean the mask, a second load lock chamber configured to receive a wafer, an exposure module configured to expose the wafer to a light source through use of the cleaned mask. A direct path is provided between the first load lock chamber and the exposure module allowing the first load lock chamber to directly couple to the exposure module without through the cleaning module.

Lithography apparatus and method using the same

A method comprises loading a wafer onto a wafer chuck of a lithography apparatus, projecting an extreme ultraviolet light through an opening of a frame structure of the lithography apparatus, onto the wafer, and introducing an airflow from an air curtain module on the wafer chuck toward the frame structure, wherein the air curtain module surrounds the wafer. The airflow forms an air curtain around the wafer, and shields the wafer from contaminants from the frame structure or a wafer stage.

SUBSTRATE TABLE, IMMERSION LITHOGRAPHIC APPARATUS AND DEVICE MANUFACTURING METHOD

A substrate table for an immersion lithographic apparatus is disclosed having a recess, configured to receive a substrate of a given size, and a fluid extraction system, configured to extract fluid from a gap between the edge of the substrate and the edge of the recess, the fluid extraction system configured such that the rate of flow of fluid extracted from a localized section of the gap is greater than the rate of flow of fluid extracted from another section of the gap.

MASK CHUCK AND MASK MANUFACTURING APPARATUS INCLUDING SAME

A mask chuck may include a base plate including a central region and an edge region surrounding the central region, a head part including a first surface connected to the edge region of the base plate and configured to move on the edge region to be close to the central region or away from the central region, and a pad part disposed on a second surface of the head part opposite to the first surface of the head part. The edge region may include a first edge region extending in a first direction, a second edge region extending in the first direction and spaced apart from the first edge region in a second direction crossing the first direction, a third edge region extending in the second direction, and a fourth edge region extending in the second direction and spaced apart from the third edge region in the first direction.

Lithographic apparatus and method

A lithographic apparatus comprising a substrate storage module having a controllable environment for protecting lithographically exposed substrates from ambient air. The substrate storage module is configured to store at least twenty substrates and the substrate storage module is an integral part of the lithographic apparatus. The substrate storage module may be used to protect substrates from ambient air during stitched lithographic exposures.

Particle traps and barriers for particle suppression

Designs are provided to reduce the possibility of contaminant particles with a large range of sizes, materials, travel speeds and angles of incidence reaching a particle-sensitive environment. According to an aspect of the disclosure, there is provided an object stage comprising first and second chambers, a first structure having a first surface, and a second structure. The second structure is configured to support an object in the second chamber, movable relative to the first structure. The second structure comprises a second surface opposing the first surface of the first structure thereby defining a gap between the first structure and the second structure that extends between the first chamber and the second chamber. The second structure further comprises a third surface within the first chamber. The object stage further comprises a trap disposed on at least a portion of the third surface, the trap comprising a plurality of baffles.

Substrate table, immersion lithographic apparatus and device manufacturing method

A substrate table for an immersion lithographic apparatus is disclosed having a recess, configured to receive a substrate of a given size, and a fluid extraction system, configured to extract fluid from a gap between the edge of the substrate and the edge of the recess, the fluid extraction system configured such that the rate of flow of fluid extracted from a localized section of the gap is greater than the rate of flow of fluid extracted from another section of the gap.

Wafer table with dynamic support pins

A method for semiconductor fabrication includes mounting a wafer onto a first wafer table. The first wafer table includes a first set of pins that support the wafer, the first set of pins having a first pitch between adjacent pins. The method further includes forming a first set of overlay marks on the wafer; and transferring the wafer onto a second wafer table. The second wafer table includes a second set of pins having a second pitch between adjacent pins. The second set of pins are individually and vertically movable, and the second pitch is smaller than the first pitch. The method further includes moving a portion of the second set of pins such that a remaining portion of the second set of pins supports the wafer and the remaining portion has the first pitch between adjacent pins.