An information processing apparatus includes a fan, a plurality of power supply units, and a reception unit. The plurality of power supply units supplies power to the fan. The reception unit receives, from the fan, a signal indicating a state of the fan. At least one of the plurality of power supply units that supplies power to the fan also supplies power to the reception unit.

An information processing apparatus includes a fan, a plurality of power supply units, and a reception unit. The plurality of power supply units supplies power to the fan. The reception unit receives, from the fan, a signal indicating a state of the fan. At least one of the plurality of power supply units that supplies power to the fan also supplies power to the reception unit.

This disclosure discloses a power supply method and a power supply device, and pertains to the field of power supply technologies. The method includes: supplying, by a power supply device, power to a load through a power supply port, where the power supply port is connected to a power receiving port of the load by using a power supply cable; and communicating, by the power supply device, with the load through a communications port, to manage a behavior of obtaining power by the load from the power supply device, where the communications port is connected to a communications port of the load by using a communications cable. In this disclosure, the power supply device is a power supply of the load and a controller of the load.

A boost and LDO hybrid converter with dual-loop control is disclosed. In some implementations, a hybrid converter includes an inductor having a first terminal to receive an input voltage and a second terminal; an n-type metal oxide semiconductor device (nMOS) having a drain coupled to the second terminal of the inductor; a p-type metal oxide semiconductor device (pMOS) having a gate, a drain, and a source, the source coupled to the second terminal of the inductor; an output capacitor having a first terminal coupled to the drain of the first pMOS; and a controller having a switch driver and a buffer, wherein the controller is configured to use the switch driver to drive the gate of the first pMOS in a boost mode and to use the buffer to drive the gate of the first pMOS in a low drop out (LDO) mode.

A boost and LDO hybrid converter with dual-loop control is disclosed. In some implementations, a hybrid converter includes an inductor having a first terminal to receive an input voltage and a second terminal; an n-type metal oxide semiconductor device (nMOS) having a drain coupled to the second terminal of the inductor; a p-type metal oxide semiconductor device (pMOS) having a gate, a drain, and a source, the source coupled to the second terminal of the inductor; an output capacitor having a first terminal coupled to the drain of the first pMOS; and a controller having a switch driver and a buffer, wherein the controller is configured to use the switch driver to drive the gate of the first pMOS in a boost mode and to use the buffer to drive the gate of the first pMOS in a low drop out (LDO) mode.

A boost and LDO hybrid converter with dual-loop control is disclosed. In some implementations, a hybrid converter includes an inductor having a first terminal to receive an input voltage and a second terminal; an n-type metal oxide semiconductor device (nMOS) having a drain coupled to the second terminal of the inductor; a p-type metal oxide semiconductor device (pMOS) having a gate, a drain, and a source, the source coupled to the second terminal of the inductor; an output capacitor having a first terminal coupled to the drain of the first pMOS; and a controller having a switch driver and a buffer, wherein the controller is configured to use the switch driver to drive the gate of the first pMOS in a boost mode and to use the buffer to drive the gate of the first pMOS in a low drop out (LDO) mode.

A boost and LDO hybrid converter with dual-loop control is disclosed. In some implementations, a hybrid converter includes an inductor having a first terminal to receive an input voltage and a second terminal; an n-type metal oxide semiconductor device (nMOS) having a drain coupled to the second terminal of the inductor; a p-type metal oxide semiconductor device (pMOS) having a gate, a drain, and a source, the source coupled to the second terminal of the inductor; an output capacitor having a first terminal coupled to the drain of the first pMOS; and a controller having a switch driver and a buffer, wherein the controller is configured to use the switch driver to drive the gate of the first pMOS in a boost mode and to use the buffer to drive the gate of the first pMOS in a low drop out (LDO) mode.

A voltage supply circuit is provided. The voltage supply circuit is capable of operating at a first mode and generates a loading current at an output node. The voltage supply circuit includes a plurality of inductors and a plurality of drier circuits. The plurality of inductors are coupled to the output node. Each inductor has an inductance value. The plurality driver circuits are coupled to the plurality of inductors respectively. The inductance value of a first inductor among the plurality of inductors is greater than the inductance values of the other inductor.

In examples, an apparatus includes a FET, first and second voltage-to-current circuits, a current selection circuit, and a comparator. The FET has first and second segments. The first segment has a first gate coupled to the first voltage-to-current circuit, a first source, and a first drain. The second segment has a second gate coupled to the second voltage-to-current circuit, a second source coupled to the first source, and a second drain coupled to the first drain. The current selection circuit has a current selection circuit output and first and second current selection inputs. The first current selection circuit input is coupled to the first voltage-to-current circuit. The second current selection circuit input is coupled to the second voltage-to-current circuit. The comparator has a comparator output and first and second comparator inputs, the first comparator input is coupled to the current selection circuit output.

Systems and methods for usage of secondary power supplies in computing environments based on risk and cost assessments are disclosed. According to an aspect, a method includes determining a risk value to a primary power source of a need to utilize a secondary power source for powering a plurality of computing devices. The method includes using the secondary power source to power a portion of the computing devices based on the determined risk value.