A comparing device includes: a first current generating circuit arranged to selectively generate a first current according to a first control signal; a second current generating circuit arranged to generate a second current; and a comparing circuit having a common node coupled to the first current generating circuit and the second current generating circuit for comparing a first input signal and a second input signal to generate an output signal according to the first current, the second current, and a second control signal.

A comparing device includes: a first current generating circuit arranged to selectively generate a first current according to a first control signal; a second current generating circuit arranged to generate a second current; and a comparing circuit having a common node coupled to the first current generating circuit and the second current generating circuit for comparing a first input signal and a second input signal to generate an output signal according to the first current, the second current, and a second control signal.

A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.

A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.

A voltage regulator can include: an input port with two terminals, and being configured to receive an input voltage; an output port with two terminals, and being configured to generate an output voltage, where the input port and the output port have a common ground potential; a group of input switches coupled in series between the two terminals of the input port, where a common node of every two adjacent input switches that form an input half-bridge topology is taken as an input switch node; at least one output half-bridge topology coupled between two terminals of the output port, where a common node of a high-side output switch and a low-side output switch in each output half-bridge topology is taken as an output switch node; and N storage capacitors, where each of the storage capacitors is coupled between one input switch node and one output switch node.

A voltage regulator can include: an input port with two terminals, and being configured to receive an input voltage; an output port with two terminals, and being configured to generate an output voltage, where the input port and the output port have a common ground potential; a group of input switches coupled in series between the two terminals of the input port, where a common node of every two adjacent input switches that form an input half-bridge topology is taken as an input switch node; at least one output half-bridge topology coupled between two terminals of the output port, where a common node of a high-side output switch and a low-side output switch in each output half-bridge topology is taken as an output switch node; and N storage capacitors, where each of the storage capacitors is coupled between one input switch node and one output switch node.

The invention relates to powering one or more devices, in particular in the context of Power-over-Ethernet (PoE). In an embodiment of the invention, it is proposed to equip each node (11) with a PD interface (22) that can signal multiples of the standard defined unity load (25 k with tolerances) during the detection process and increase the load during a sequence of detection attempts. In that way, several nodes (11) can share one PSE outlet and determine the number of neighboring loads (11). At the same time, each node (11) will offer full functionality during normal stand-alone wiring. This powering concept can be combined with full or limited data communication capabilities.

An example system includes a failure detection circuit. The failure detection circuit is to detect a failure of a first power source electrically coupled to a first load. The failure detection circuit is to output a first signal indicating the detection of the failure of the first power source. The system also includes a current regulating circuit. The current regulating circuit is electrically coupled to the failure detection circuit. The current regulating circuit is to electrically couple a second power source to the first load based on the first signal output by the failure detection circuit. The current regulating circuit is to restrict a first current from the second power source.

A complementary metal-oxide-semiconductor (CMOS) switching system with increased supply rejection is disclosed. The system comprises a voltage regulator and a CMOS circuit. The voltage regulator receives a supply voltage and generates a regulated voltage by regulating an amplitude of the received supply voltage. The CMOS circuit includes an input terminal to receive a first voltage, switching circuitry to selectively couple the CMOS circuit to the voltage regulator in one of a plurality of configurations, and an output terminal to output a second voltage based at least in part on the first voltage and the regulated voltage when the CMOS circuit is coupled to the voltage regulator in a first configuration of the plurality of configurations.

A complementary metal-oxide-semiconductor (CMOS) switching system with increased supply rejection is disclosed. The system comprises a voltage regulator and a CMOS circuit. The voltage regulator receives a supply voltage and generates a regulated voltage by regulating an amplitude of the received supply voltage. The CMOS circuit includes an input terminal to receive a first voltage, switching circuitry to selectively couple the CMOS circuit to the voltage regulator in one of a plurality of configurations, and an output terminal to output a second voltage based at least in part on the first voltage and the regulated voltage when the CMOS circuit is coupled to the voltage regulator in a first configuration of the plurality of configurations.