For example, a linear power supply includes an output transistor connected between an input terminal of an input voltage and an output terminal of an output voltage, an internal power supply configured to step down the input voltage to generate a predetermined internal power supply voltage, a reference voltage generator configured to generate a predetermined reference voltage from the internal power supply voltage, an amplifier configured to generate a drive signal for the output transistor such that a feedback voltage in accordance with the output voltage is equal to the reference voltage, a drive current generator configured to generate a drive current for the amplifier, and a drive current controller configured to detect a variation of the internal power supply voltage to variably control the drive current.

A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.

Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.

A linear regulator for applications with low area constraint resulting in limited load decoupling capacitance that introduces a compensating zero in the regulator loop to counteract the loss of phase margin and further introduces a feed-forward noise cancellation path operating over a wide frequency range covering a first package resonance frequency. The feed-forward path has low power consumption and improves the power-supply rejection ratio.

Embodiments of a power stage with vertical integration for high-density, low-noise voltage regulators are described. In some embodiments, an Information Handling System (IHS) may include: a processor; and a multi-phase voltage regulator (VR) coupled to the processor, where the multi-phase VR comprises at least one power stage, and where the at least one power stage includes: a High-Side Field-Effect Transistor (HSFET) die mounted on a leadframe; a Low-Side FET (LSFET) die mounted on the leadframe; at least one decoupling capacitor mounted on the leadframe; and a driver circuit mounted on a clip, where the clip overlays at least a portion of the HSFET die and the LSFET die.

A circuit includes a digital-to-analog converter (DAC) having a DAC input and a DAC output. The circuit includes a reference voltage (VREF) generator having a VREF generator input, a VREF generator output, and a VREF power supply input. The VREF generator output is coupled to the DAC input. A voltage regulator has a voltage regulator input and a voltage regulator output. The voltage regulator output is coupled to the DAC. A clamp circuit has a first clamp circuit input, a second clamp circuit input, and a clamp circuit output. The first clamp circuit input is coupled to the voltage regulator input, and the clamp circuit output is coupled to the VREF power supply input. The second clamp circuit input is coupled to the voltage regulator output. The clamp circuit includes a source-follower circuit having the second clamp circuit input.

Methods, apparatus, systems, and articles of manufacture are disclosed to enable Digital Satellite Equipment Control (DiSEqC) communication between an antenna and a processor. An example apparatus includes a receiver to be coupled to an antenna by a cable and configured to bidirectionally communicate with the antenna via a communication signal having a periodic waveform, wherein the receiver further includes a low dropout regulator (LDO) pass transistor to be coupled to the cable and configured to generate a current signal based on the periodic waveform of the communication signal, a current envelope detector circuit coupled to the LDO pass transistor configured to generate a voltage signal based on the current signal, and a processor. The processor is coupled to the current envelope detector circuit and configured to process the voltage signal generated by the current envelope detector.

A power regulator is applied to regulate a work frequency of a central processing unit and the power regulator comprises a power resister, a voltage amplifier and an analog-to-digital converter. The power resister is coupled to a load to generate a first voltage. The voltage amplifier is coupled to the power resister to output a second voltage. The analog-to-digital converter is coupled to the voltage amplifier, converts the second voltage into a control signal and transmits the control signal to the central processing unit. The control signal is switched between a first level and a second level according to a value of the second voltage.

A linear regulator for applications with low area constraint resulting in limited load decoupling capacitance that introduces a compensating zero in the regulator loop to counteract the loss of phase margin and further introduces a feed-forward noise cancellation path operating over a wide frequency range covering a first package resonance frequency. The feed-forward path has low power consumption and improves the power-supply rejection ratio.

Embodiments of the invention provide for a system, method, and controller for operating a harmonic regulator with loop delay compensation. Some embodiments include receiving, at a controller, voltage feedback from a power system, and applying a harmonic regulator to each distortion frequency to be compensated. Embodiments also include applying a predetermined delay to an output of the harmonic regulator, scaling the delayed output and adding it to a power source voltage reference waveform, and providing condition power to a load, using the conditioned power source voltage reference waveform.