A method and apparatuses for power regulation using an extended current limit are disclosed. The power regulator detects an occurrence of an output current of the regulator exceeding a first current limit, triggers an extended current limit timer based on the detected occurrence, regulates the output current according to a second current limit higher than the first current limit based on a duration of the extended current limit timer, and regulates the output current according to the first current limit based on an expiration of the duration of the extended current limit timer.

A switching regulator circuit incorporates an offset circuit, connected in a control loop of the regulator circuit, that, in response to a signal indicating an imminent load current step, adjusts a duty cycle of a power switch for the current step prior to the regulator circuit responding to a change in output voltage due to the current step. In one embodiment, a load controller issues a digital signal shortly before a load current step. The digital signal is decoded and converted to an analog offset signal in a feedback control loop of the regulator to immediately adjust a duty cycle of the switch irrespective of the output voltage level. By proper timing of the offset, output voltage ripple is greatly reduced. The current offset may also be used to rapidly change the output voltage in response to an external signal requesting a voltage step.

Power amplifier circuitry includes an amplifier stage, a non-linear compensation network, and non-linear compensation control circuitry. The amplifier stage includes an input and an output, and is configured to receive an input signal at the input and provide an amplified output signal at the output. The non-linear compensation network is coupled between the input and the output of the amplifier stage. The non-linear compensation control circuitry is coupled to the non-linear compensation network and one or more of the input and the output of the amplifier stage. The non-linear compensation control circuitry is configured to adjust a capacitance of the non-linear compensation network to cancel a parasitic capacitance associated with the amplifier stage and thus reduce AM-PM distortion.

A floating-rail reference generator and method of operating the same are provided. Generally, the generator includes a tracking current source coupled in series with a current scaling resistor between an input voltage (V.sub.BAT) and ground. The tracking current source is operable to receive a reference voltage and couple a tracking current through the resistor to produce a floating-rail reference voltage (V.sub.SSHV_REF) at an output between the tracking current source and scaling resistor, wherein: V.sub.SSHV_REF=((V.sub.BAT-V.sub.GS)/k).Math.1/R.Math.k.Math.R, where V.sub.GS is a desired constant potential difference between V.sub.BAT and V.sub.SSHV_REF, k is a voltage scaling ratio, and R is a resistance of the current scaling resistor. In some embodiments, the tracking current source includes a transistor coupled between V.sub.BAT and the output, and controlled by a differential amplifier.

A circuit includes a first resistive element having a first terminal coupled to an input node to receive a negative voltage, a second resistive element having a first terminal coupled to a first power supply terminal, and a third resistive element having a first terminal coupled to the first power supply terminal. A first current mirror includes a first transistor coupled to a second terminal of the second resistive element and a second transistor coupled to a second terminal of the third resistive element and the first transistor, wherein the output node corresponds to the second terminal of the third resistive element. A second current mirror includes a third transistor coupled to the first transistor and a fourth transistor coupled to the second transistor, third transistor, and a second terminal of the first resistive element. The circuit converts the negative voltage to the positive proportion voltage.

A processor system includes first and second regulators for regulating an adjusted supply voltage. In one embodiment, the regulator system comprises a digital low-dropout (DLDO) control system comprising first and second regulators that generate a plurality of control signals to regulate an adjusted power supply voltage and that generate a charge when a droop level falls below a droop threshold value. The first regulator implements a first control loop and the second regulator implements a second and much faster acting control loop. A supply adjustment block with the two regulators and control loops are provided for each processor core allowing different cores to have different regulated supply levels all based on one common supply.

A cascaded thin-oxide N-Well voltage steering circuit includes a reference voltage generator that outputs a reference voltage within a range of first and second supply voltages, a first voltage steering circuit that outputs a higher available one of the reference voltage and the second supply voltage as an interim voltage, and a second voltage steering circuit that outputs a higher available one of the first voltage and the interim voltage at an output of the second voltage steering circuit. The interim voltage is applied to N-wells of PMOS transistors of the first voltage steering circuit. The output of the second voltage steering circuit is applied to N-wells of PMOS transistors of the second voltage steering circuit. The output of the second voltage steering circuit may also be applied to N-wells of PMOS transistors of other circuitry. The cascaded thin-oxide N-Well voltage steering circuit may consist substantially of thin-oxide PMOS transistors.

A power control device includes: an output voltage controller configured to control an output voltage based on a feedback voltage corresponding to the output voltage; and an overvoltage protector configured to continue or stop the operation of the output voltage controller based on a first detection result of whether the output voltage has exceeded an output voltage threshold value and a second detection result of whether the feedback voltage has fallen to or below a feedback voltage threshold value.

A regulator for providing a load current at a regulator output voltage to a load at an output of the regulator is described. The regulator has a differential input stage to provide a differential output voltage based on a reference voltage and based on the regulator output voltage. Furthermore, the regulator has an output driver to generate a control signal based on the differential output voltage. In addition, the regulator has a pass transistor to provide the load current in dependence of the control signal. The regulator also has clamping circuitry to sense an overvoltage indication which indicates that the pass transistor is being turned off. Furthermore, the clamping circuitry clamps the differential output voltage to a clamping voltage, if the overvoltage indication indicates that the pass transistor is being turned off.

A regulator for providing a load current at a regulator output voltage to a load at an output of the regulator is described. The regulator has a differential input stage to provide a differential output voltage based on a reference voltage and based on the regulator output voltage. Furthermore, the regulator has an output driver to generate a control signal based on the differential output voltage. In addition, the regulator has a pass transistor to provide the load current in dependence of the control signal. The regulator also has clamping circuitry to sense an overvoltage indication which indicates that the pass transistor is being turned off. Furthermore, the clamping circuitry clamps the differential output voltage to a clamping voltage, if the overvoltage indication indicates that the pass transistor is being turned off.