A voltage regulator that includes a first amplifier, a second amplifier, a summer, and a transistor is presented. The first amplifier has a first gain and a first frequency bandwidth, and is configured to generate a first voltage output. The second amplifier has a second gain that is lower than the first gain and a second frequency bandwidth that is higher than the first frequency bandwidth, and is configured to generate a second voltage output. The summer is configured to generate a summed voltage output. The transistor is connected to the summer and configured to generate a regulated voltage based on the summed voltage output of the summer.

A voltage regulator that includes a first amplifier, a second amplifier, a summer, and a transistor is presented. The first amplifier has a first gain and a first frequency bandwidth, and is configured to generate a first voltage output. The second amplifier has a second gain that is lower than the first gain and a second frequency bandwidth that is higher than the first frequency bandwidth, and is configured to generate a second voltage output. The summer is configured to generate a summed voltage output. The transistor is connected to the summer and configured to generate a regulated voltage based on the summed voltage output of the summer.

Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.

Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.

One or more sampling parameters of an application associated with a downstream voltage regulator may be determined. A power supply rejection ratio (“PSRR”) and a switching frequency of an upstream voltage regulator may be dynamically adjusted based on the sampling parameters of the application associated with the downstream voltage regulator. The sampling parameters may include a noise level and a workload of the selected application.

A low-dropout regulator for low voltage applications includes a buffer circuit being arranged between an output terminal of an error amplifier and a control node of a pass device. The buffer circuit includes a driver having a first transistor being embodied as an NMOS transistor. The output terminal of the error amplifier is coupled to the control node of the first transistor. The control node of the pass device is coupled to an internal node of a first current path including the first transistor. The low-dropout regulator has high load capability, even if an input supply voltage is very low.

A low-dropout regulator for low voltage applications includes a buffer circuit being arranged between an output terminal of an error amplifier and a control node of a pass device. The buffer circuit includes a driver having a first transistor being embodied as an NMOS transistor. The output terminal of the error amplifier is coupled to the control node of the first transistor. The control node of the pass device is coupled to an internal node of a first current path including the first transistor. The low-dropout regulator has high load capability, even if an input supply voltage is very low.

A low drop-out (LDO) regulator includes a power transistor, an error amplifier and a droop adjusting circuit. The power transistor regulates a driving voltage based on a gate voltage of a gate node to provide an output voltage at an output node. The error amplifier outputs the gate voltage by amplifying a voltage difference between a reference voltage and a feedback voltage proportional to the output voltage. The droop adjusting circuit is connected between the gate node and the output node, is coupled to the output voltage, and adjusts the gate voltage to compensate for a change of the output voltage based on a change of a load current which is provided to a load from the output node.

A low drop-out (LDO) regulator includes a power transistor, an error amplifier and a droop adjusting circuit. The power transistor regulates a driving voltage based on a gate voltage of a gate node to provide an output voltage at an output node. The error amplifier outputs the gate voltage by amplifying a voltage difference between a reference voltage and a feedback voltage proportional to the output voltage. The droop adjusting circuit is connected between the gate node and the output node, is coupled to the output voltage, and adjusts the gate voltage to compensate for a change of the output voltage based on a change of a load current which is provided to a load from the output node.

A low-dropout regulator system includes a low-dropout regulator. A comparator circuit generates a comparison voltage according to a reference voltage and a feedback voltage. An amplifier circuit generates an amplifying voltage according to the comparison voltage. A transistor receives an input voltage and is controlled by the amplifying voltage to generate an output voltage at an output terminal. A first resistor circuit is coupled between a first node and a ground terminal. A second resistor circuit is coupled between the output terminal and the first node. At a start-up timing point of the low-dropout regulator, a resistance value of the second resistor circuit is a first resistance value. After the input voltage reaches a maximum voltage, the resistance value of the second resistor circuit is a second resistance value. The second resistance value is larger than the first resistance value.