An LDO power supply circuit includes an operational amplifier, a first transistor, and a resistance feedback network including a first branch and a second branch. A negative electrode input end of the operational amplifier connects a control voltage. An output end of the operational amplifier connects a gate electrode of the first transistor. A source electrode of the first transistor connects a power supply voltage. A positive electrode input end of the operational amplifier and a drain electrode of the first transistor are respectively an input end and an output end of the LDO power supply circuit. The resistance feedback network connects between the drain electrode of the first transistor and the positive electrode input end of the operational amplifier. A first feedback coefficient formed by the first branch is different from a second feedback coefficient formed by the second branch. The present disclosure further provides a power amplifier.

An LDO power supply circuit includes an operational amplifier, a first transistor, and a resistance feedback network including a first branch and a second branch. A negative electrode input end of the operational amplifier connects a control voltage. An output end of the operational amplifier connects a gate electrode of the first transistor. A source electrode of the first transistor connects a power supply voltage. A positive electrode input end of the operational amplifier and a drain electrode of the first transistor are respectively an input end and an output end of the LDO power supply circuit. The resistance feedback network connects between the drain electrode of the first transistor and the positive electrode input end of the operational amplifier. A first feedback coefficient formed by the first branch is different from a second feedback coefficient formed by the second branch. The present disclosure further provides a power amplifier.

A voltage regulator includes a main driving stage circuit, a first pre-driving circuit, a plurality of auxiliary driving stage circuits, a second pre-driving circuit, and a comparison and decoding circuit. The main driving stage circuit provides a main driving current of an output voltage according to a first control signal. Each of the auxiliary driving stage circuits determines whether to provide an auxiliary driving current of the output voltage according to a second control signal. The second pre-driving circuit generates the second control signal according to an enable signal. The comparison and decoding circuit generates a simulated driving current and generates a load current according to a reference current and a counting code, compares the simulated driving current with the load current to generate a comparison result, and generates the enable signal by decoding the comparison result. The counting code is generated according to the comparison result.

A device performing a power gating operation includes a switch control signal generation circuit and a power gating circuit. The switch control signal generation circuit controls an operation that generates a first switch control signal and a second switch control signal from a mode signal based on a comparison result of a first power source voltage and a second power source voltage until a mode register set operation is performed after a power-up period ends. The power gating circuit drives a power source voltage to the first power source voltage or the second power source voltage based on the first switch control signal and the second switch control signal.

A Low Dropout Regulator (LDO) with Less Quiescent Current in the Dropout Region is described, including an error amplifier configured to compare a reference voltage to an LDO output voltage across a resistive divider, a current mirror configured to mirror a first output of the error amplifier to a first and second output of the current mirror, and a comparator configured to compare the LDO output voltage to a second output of the error amplifier, which has been compared to the second output of the current mirror, and configured to output a control voltage to the error amplifier, where a low quiescent current is maintained when an LDO input voltage is near or less than the LDO output voltage.

A Low Dropout Regulator (LDO) with Less Quiescent Current in the Dropout Region is described, including an error amplifier configured to compare a reference voltage to an LDO output voltage across a resistive divider, a current mirror configured to mirror a first output of the error amplifier to a first and second output of the current mirror, and a comparator configured to compare the LDO output voltage to a second output of the error amplifier, which has been compared to the second output of the current mirror, and configured to output a control voltage to the error amplifier, where a low quiescent current is maintained when an LDO input voltage is near or less than the LDO output voltage.

In certain aspects, a driver includes a pull-down transistor coupled between an output and a ground, a pull-up n-type field effect transistor (NFET) coupled between a first voltage rail and the output, and a pull-up p-type field effect transistor (PFET) coupled between the first voltage rail and the output. The driver also includes a first switch coupled between a gate of the pull-up NFET and the ground, and a second switch coupled between a gate of the pull-up PFET and a second voltage rail.

The present invention provides a reference voltage generating circuit. The reference voltage generating circuit includes a charge supply circuit providing a first reference voltage during a first period; and a voltage supply circuit providing a second reference voltage during a second period. The voltage supply circuit does not provide the second reference voltage during the first period.

The present invention provides a reference voltage generating circuit. The reference voltage generating circuit includes a charge supply circuit providing a first reference voltage during a first period; and a voltage supply circuit providing a second reference voltage during a second period. The voltage supply circuit does not provide the second reference voltage during the first period.

A digital low dropout (LDO) voltage regulator enabling on-chip fine-grain power management in multi-core microprocessor and system-on-a-chip platforms to increase system level energy efficiency. Its design synthesizability with automatic placement and routing enables per-core dynamic voltage and frequency scaling with quick design turnaround. To enable per-core voltage regulation, the digital LDO is designed in a 65 nm complementary metal-oxide-semiconductor process. It exhibits core-level high load current driving capability of up to 125 mA and a large voltage regulation range of 0.15 V to 1.15 V.