Some embodiments relate to a device disposed on a semiconductor substrate. The semiconductor substrate includes a base region and a crown structure extending upwardly from the base region. The crown structure is narrower than the base region. A plurality of fins extend upwardly from an upper surface of the crown structure. A gate dielectric material is disposed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode is disposed along sidewall portions of the gate dielectric material. An uppermost surface of the conductive electrode resides below the upper surfaces of the plurality of fins.

Some embodiments relate to a device disposed on a semiconductor substrate. The semiconductor substrate includes a base region and a crown structure extending upwardly from the base region. The crown structure is narrower than the base region. A plurality of fins extend upwardly from an upper surface of the crown structure. A gate dielectric material is disposed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode is disposed along sidewall portions of the gate dielectric material. An uppermost surface of the conductive electrode resides below the upper surfaces of the plurality of fins.

A correction current output circuit comprises a first voltage dividing circuit for generating a voltage in which an output voltage from a bandgap reference voltage circuit is divided in multiple stages, first and second correction circuits connected between a power supply and a ground, and a second voltage dividing circuit for dividing the above voltage in multiple stages in a path in which a positive temperature characteristic voltage is generated with the band gap reference voltage circuit. Current output terminals of a the second transistor of the first correction circuit and a first transistor of the second correction circuit are connected to a common connection point, and a current for correcting the temperature characteristic of a reference voltage generation circuit is output from the common connection point.

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

A power manager circuit is provided. The power manager circuit includes a bandgap reference circuit, first and second monitoring circuits, and a reference buffer. The bandgap reference circuit generates a first voltage, based on an external voltage that is external to the power manager circuit. The first monitoring circuit determines a logical value of a first alarm signal, based on whether a first voltage level of the first voltage is within a first range. The reference buffer generates a second voltage, based on the first voltage. The second monitoring circuit determines a logical value of a second alarm signal, based on whether a second voltage level of the second voltage is within a second range.

A power manager circuit is provided. The power manager circuit includes a bandgap reference circuit, first and second monitoring circuits, and a reference buffer. The bandgap reference circuit generates a first voltage, based on an external voltage that is external to the power manager circuit. The first monitoring circuit determines a logical value of a first alarm signal, based on whether a first voltage level of the first voltage is within a first range. The reference buffer generates a second voltage, based on the first voltage. The second monitoring circuit determines a logical value of a second alarm signal, based on whether a second voltage level of the second voltage is within a second range.

A current detection circuit, a semiconductor device and a semiconductor system which are capable of improving current detection accuracy are provided. According to one embodiment of the invention, a current detection circuit includes a resistive element to convert an input current supplied from outside into an input voltage, a constant-current source, a resistive element to convert an output current of the constant-current source into a reference voltage, and an AD converter to AD-convert the input voltage using the reference voltage.

A current detection circuit, a semiconductor device and a semiconductor system which are capable of improving current detection accuracy are provided. According to one embodiment of the invention, a current detection circuit includes a resistive element to convert an input current supplied from outside into an input voltage, a constant-current source, a resistive element to convert an output current of the constant-current source into a reference voltage, and an AD converter to AD-convert the input voltage using the reference voltage.

Disclosed herein is an apparatus that includes a first external terminal supplied with a first power potential, a second external terminal supplied with a second power potential different from the first power potential, a first transistor connected between the first external terminal and an internal power line, a second transistor connected between the second external terminal and the internal power line, and a first circuit configured to turn the first transistor OFF during at least a first period until the second power potential is supplied after the first power potential is supplied.

Disclosed herein is an apparatus that includes a first external terminal supplied with a first power potential, a second external terminal supplied with a second power potential different from the first power potential, a first transistor connected between the first external terminal and an internal power line, a second transistor connected between the second external terminal and the internal power line, and a first circuit configured to turn the first transistor OFF during at least a first period until the second power potential is supplied after the first power potential is supplied.