Systems and methods for a split phase accumulator having a plurality of sub phase accumulators are provided. Each sub phase accumulator receives a portion of a frequency control word. The first sub phase accumulator includes a first register and the remaining sub phase accumulators include a register and an overflow register. At each discrete point in time, the first sub phase accumulator is configured to be responsive to the first portion of the frequency control word at that discrete point in time and to the first sub phase accumulator value at the immediately previous discrete point in time, and each of the remaining sub phase accumulators is configured to be responsive to a value of its corresponding portion of the frequency control word at that discrete point in time and to the same second sub phase accumulator value at the immediately previous discrete point in time.

According to some embodiments, a system comprises a memory configured to store protection waveform data, and a comparator waveform generator configured to access the memory to generate a protection waveform from the protection waveform data based on a trigger associated with the system, receive a measured system characteristic waveform, and generate a fault interrupt responsive to a comparison between the measured system characteristic waveform and the protection waveform violating a fault condition.

Apparatuses, systems, and methods for sine wave generation based on a flexible pulse width modulation (PWM) technique. An exemplary apparatus may comprise a sine wave generator circuitry and a pulse width modulation timer circuitry coupled to the sine wave generator circuitry. The sine wave generator circuitry may comprise a phase accumulator circuitry and a phase to amplitude conversion circuitry coupled to the phase accumulator circuitry. The phase accumulator circuitry may be configured to receive a digital input value and output phase values. The phase to amplitude conversion circuitry may be configured to receive the phase values and output digital sine values. The pulse width modulation timer circuitry may be configured to receive the digital sine values and output at least one pulse width modulation signal for generation of an analog carrier wave signal. A frequency of the analog carrier wave signal may be based on the digital input value.

A DDS circuit includes a phase accumulator circuit. The phase accumulator circuit includes a clock input being configured to receive a clock signal. The phase accumulator circuit includes a frequency tuning register configured to receive a frequency tuning word (FTW), and a phase shift register configured to receive a phase shift word (PSW). The phase accumulator circuit also includes a phase increment sub-circuit configured to increment a phase signal output by the phase accumulator circuit by a predetermined phase increment based on the clock signal and/or based on the FTW. The phase accumulator circuit further includes a feedback path configured to feed back the phase signal to the phase increment sub-circuit. The phase accumulator circuit further includes a phase correction sub-circuit configured to adapt the phase signal fed back to the phase increment sub-circuit based on the phase shift word.