A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.

Controlling server power usage in a data center is provided. Power usage among a plurality of server racks in active mode processing a set of workloads in the data center is managed. It is detected that a new server rack in standby mode is being added to the plurality of server racks. It is ensured that the new server rack in the standby mode is properly controlled and monitored prior to transitioning the new server rack to the active mode. It is determined whether power safety criteria are met to safely join the new server rack to the plurality of server racks prior to transitioning the new server rack from the standby mode to the active mode. The new server rack is transitioned to the active mode in without exceeding a power budget for the plurality of server racks in response to determining that the power safety criteria are met.

A master-slave interchangeable power supply device, a power supply method, a host with the master-slave interchangeable power supply device, and a computer-readable storage medium for use in execution of the power supply method are provided. Upon receipt of a start command, a power control module and a power supply unit of the power supply device operate in a master mode and a slave mode respectively, and then the power supply device provides a working power to a master device to effect related configuration of the power supply device, so as to allow the power control module to switch to the slave mode and allow the working power to be provided to the master device. Therefore, given compliance with a specification of a communication bus, the power control module and the power supply unit, which function as peripheral devices, can perform a communicative function.

A master-slave interchangeable power supply device, a power supply method, a host with the master-slave interchangeable power supply device, and a computer-readable storage medium for use in execution of the power supply method are provided. Upon receipt of a start command, a power control module and a power supply unit of the power supply device operate in a master mode and a slave mode respectively, and then the power supply device provides a working power to a master device to effect related configuration of the power supply device, so as to allow the power control module to switch to the slave mode and allow the working power to be provided to the master device. Therefore, given compliance with a specification of a communication bus, the power control module and the power supply unit, which function as peripheral devices, can perform a communicative function.

An electronic circuit unit includes a trigger circuit and a circuit module. The trigger circuit includes a semiconductor switching element configured to output a switching pulse signal in response to an external trigger signal, a load resistor for the semiconductor switching element, a one-shot pulse circuit configured to convert the switching pulse signal into a one-shot pulse with a predetermined pulse width, and a forcible-reset circuit connected to an input side of the semiconductor switching element. The one-shot pulse circuit includes a coupling capacitor connected to an input side of the semiconductor switching element and a charging resistor for the coupling capacitor. The pulse width of the one-shot pulse is determined by a time constant of the coupling capacitor and the charging resistor. The forcible-reset circuit is configured to temporarily input an on-voltage to the semiconductor switching element so as to forcibly switch the circuit module to the operating mode.

Techniques and mechanisms for providing a thread scheduling hint to an operating system of a processor which comprises first cores and second cores. In an embodiment, the first cores are of a first type which corresponds to a first range of sizes, and the second cores are of a second type which corresponds to a second range of sizes smaller than the first range of sizes. A power control unit (PCU) of the processor is to detect that an inefficiency, of a first operational mode of the processor, would exist while an indication of an amount of power, to be available to the processor, is below a threshold. Based on the detecting, the PCU hints to an executing software process that a given core is to be included in, or omitted from, a pool of cores available for thread scheduling. The hint indicates the given core based on a relative prioritization of the first core type and the second core type.

An event recorder for a power supply and a method thereof are provided. The event recorder method includes: selecting an event combination; based on the selected event combination, performing a setting step to set a trigger source combination and a record data combination, wherein the setting step further comprises any combination of the following: setting a record data type combination, setting a trigger type combination, setting a resolution combination, and setting a logic combination; and in response to a logic combination result of the trigger source combination, storing the record data combination in a storage unit.

An event recorder for a power supply and a method thereof are provided. The event recorder method includes: selecting an event combination; based on the selected event combination, performing a setting step to set a trigger source combination and a record data combination, wherein the setting step further comprises any combination of the following: setting a record data type combination, setting a trigger type combination, setting a resolution combination, and setting a logic combination; and in response to a logic combination result of the trigger source combination, storing the record data combination in a storage unit.

An information handling system includes a failsafe circuit connected to a first power control interconnect conductor, to a second power control interconnect conductor, and to a processor status interconnect conductor. A processor may provide a first level indicating an operational status of the processor to the processor status interconnect conductor when the processor is operational, and provide a second level indicating a non-operational status of the processor to the processor status interconnect conductor when the processor is non-operational. The failsafe circuit may assure, upon provision of the second level to the processor status interconnect conductor, that the first power control interconnect conductor will be in a first failsafe state and the second power control interconnect conductor will be in a second failsafe state.

An information handling system includes a failsafe circuit connected to a first power control interconnect conductor, to a second power control interconnect conductor, and to a processor status interconnect conductor. A processor may provide a first level indicating an operational status of the processor to the processor status interconnect conductor when the processor is operational, and provide a second level indicating a non-operational status of the processor to the processor status interconnect conductor when the processor is non-operational. The failsafe circuit may assure, upon provision of the second level to the processor status interconnect conductor, that the first power control interconnect conductor will be in a first failsafe state and the second power control interconnect conductor will be in a second failsafe state.