A wearable electronic device includes a sensor module, a processor, a display controller, and a display, where the sensor is configured to: collect data, generate a sensor signal that represents a feature of data of currently collected data, and send the sensor signal to the processor, the processor is configured to: determine, according to the received sensor signal, a manner to display that is corresponding to the feature of data represented by the sensor signal and is of the display, generate a display control signal, and send the display control signal to the display controller, and the display controller is configured to control, according to the display control signal, the display to display.

In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

A memory chip includes at least two memory blocks. In a method for controlling power supply for the memory blocks of the memory chip, each memory block receives a command for switching to standby mode. The commands are issued, for example by a processor, separately for each memory block in order to be able to individually place the memory block in standby mode.

A display device includes a display panel that includes a plurality of pixels, a touch panel that includes a plurality of driving lines and a plurality of sensing lines, a display driver that drives the display panel at a first display frame rate in a normal driving mode, and that drives the display panel at a second display frame rate lower than the first display frame rate in a low power driving mode, and a touch controller that drives the touch panel with a mutual capacitance sensing method in the normal driving mode, and that drive the touch panel with a self capacitance sensing method in the low power driving mode.

Systems and methods for peer data storage device messaging over a control bus for power management are disclosed. Storage devices may include a host interface configured to connect to a host system and a control bus interface to connect to a control bus. Peer data storage devices may establish peer communication through the control bus interface, determine a power state, receive a power change indicator from a peer data storage device, and initiate a change in their power state. The peer data storage devices may manage their collective power as a power pool and increase or decrease power use without host intervention.

A wireless instrument area network node employs an internal force sensor arrangement to detect user-provided force on the node and initiate a node operation, such as wake the node from a sleep state or low power mode to a more power-hungry awake and processing state. The internal force sensor avoids the need to provide external buttons, a screen, and the like on the surface of the node that could lead to intrusion of fluids, gases, or other unwanted substances into the node. In some embodiments, the internal sensor may include a microswitch that has sufficient sensitivity to detect even a very small amount of deflection resulting from, for example, a hand touch. In some embodiments, the internal sensor may include a piezoelectric sensor that has similarly high deflection sensitivity. Multiple such deflection detectors may be at different angles to one another deployed to provide greater directional coverage for the deflection.

Disclosed are self-checkout terminals and systems and methods for controlling the same. The systems and methods may include receiving a first image of the customer queuing area from the first camera and determining that a customer is in the customer queuing area. A first wakeup signal may be transmitted to one of the self-checkout terminals when the customer is in the customer queuing area. A second image of the customer queuing area may be received from the first camera and a determination may be made that the customer queuing area is void of customers. A first sleep signal may be transmitted to the one of the self-checkout terminals when the customer queuing area is void of the customers.

An electronic device has a memory functional block that includes memory circuits and a memory physical layer (PHY) functional block with core logic that controls operations in the memory functional block, a memory PHY voltage regulator, a system voltage regulator, and a controller. The electronic device also includes a switch having an input coupled to an output of the memory PHY voltage regulator, another input coupled to an output of the system voltage regulator, and an output coupled to a power supply input of the core logic. The controller sets the switch so that electrical power is provided from the memory PHY voltage regulator to the core logic in a full power operating state. The controller sets the switch so that electrical power is provided from the system voltage regulator to the core logic in one or more low power operating states.

The invention introduces a non-transitory computer-readable storage medium for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.

In accordance with an embodiment, an integrated driver circuit includes: a first connection and a second connection configured to be connected to a control chip; at least one bus connection configured to be connected to a bus line; and a control circuit. The control circuit is configured to operate in a first mode or a second mode; to output a reception signal at the second connection in the second mode, where the reception signal represents a bus signal received at the bus connection; to assume a state of low power consumption in the first mode; to change from the first mode to the second mode when a first command is detected at the first connection or at the second connection; and to change from the second mode to the first mode when the bus signal does not indicate any data for a predefined period of time.