Patent classifications
G06F1/3234
Display apparatus with intelligent user interface
A display apparatus includes presence detection circuitry for detecting an individual in proximity to the display apparatus; a display for displaying video content and a user interface; a processor in communication with the user input circuitry, the display, and the search history database; and non-transitory computer readable media in communication with the processor that stores instruction code. The instruction code is executed by the processor and causes the processor to: a) determine, from the presence detection circuitry, a user in proximity of the display apparatus; b) determine one or more program types associated with the user; c) determine available programs that match the predicted one or more programs; and d) update the user interface to depict a listing of one or more of the available programs that match the predicted one or more programs.
Fractional frequency divider and flash memory controller
The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
Device and method for efficient transitioning to and from reduced power state
Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.
POWER GOVERNANCE OF PROCESSING UNIT
Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.
SYSTEMS AND METHODS FOR ADAPTIVE POWER MULTIPLEXING
A system on chip (SOC) comprising: first memory block and a second memory block; a processing unit coupled to the first memory block and the second memory block; a first power multiplexor disposed between the first memory block and the second memory block and coupled to a first power rail configured to provide an operating voltage to both the first memory block and the second memory block; and enable logic circuitry disposed at a periphery of the SOC away from the first memory block and the second memory block, the enable logic being coupled to control terminals of the first power multiplexor.
OPTIMIZING MOBILE NETWORK TRAFFIC COORDINATION ACROSS MULTIPLE APPLICATIONS RUNNING ON A MOBILE DEVICE
A mobile device allows transmission of additional outgoing application data requests in response to occurrence of receipt of data transfer from a remote entity, user input in response to a prompt displayed to the user, and a change in a background status of an application executing on the mobile device. Additional outgoing application data requests are foreground application requests.
ELECTRONIC DEVICE AN METHOD FOR OPERATING ELECTRONIC DEVICE
An electronic device may include a flexible display, a battery, a memory, and a processor operatively connected to the flexible display, the battery, and the memory. The processor may be configured to: when the state of charge of the battery is a specified value or less, identify a current form factor of the flexible display; determine at least one form factor of the flexible display that can reduce power consumption of the battery; and provide information on the at least one form factor of the flexible display. Various other embodiments understood through the specification are also possible.
Storage apparatus and electronic device
A storage apparatus includes a control chip, a storage chip, a power interface configured to receive a first voltage, a first variable-voltage circuit. An input end of the first variable-voltage circuit is coupled to the power interface. The first variable-voltage circuit is configured to convert the first voltage into a second voltage, and provide the second voltage to the control chip and a second variable-voltage circuit, where an input end of the second variable-voltage circuit is coupled to the power interface. The second variable-voltage circuit is configured to convert the first voltage into a third voltage and provide the third voltage to the control chip and the storage chip.
PERIPHERAL INTERFACE POWER ALLOCATION
Examples are disclosed that relate to allocating power to peripheral device interfaces. One example provides, at a computing device, a method, comprising obtaining a measurement of power consumption by one or more peripheral devices, and based at least on the measurement and on a maximum power tolerance of a power source, allocating to each respective interface a minimum portion of power output from the power source. The method further comprises rendering a remainder of the maximum power tolerance available for consumption by one or more processors, the remainder including the maximum power tolerance minus a sum of the minimum portions, where the remainder and a system portion of power output are available for consumption by the one or more processors, and where a performance attribute of the one or more processors is not throttled while total power consumption does not exceed a threshold power output from the power source.
Touch display apparatus and sensing method of the same for identifying different touch sources and reducing power consumption
A sensing method includes sensing a first touch source at a first time point; transferring a first sensing signal of the first touch source to a CPU at the first time point; sensing a second touch source at a second time point; transferring a second sensing signal of the second touch source to the CPU at the second time point; stopping transferring the second sensing signal at a third time point, and the second touch source is away from the touch display device at a fourth time point; and the second time point is earlier than the third time point, the third time point is earlier than the fourth time point, and the first touch source is different from the second touch source.