One or more media scan parameters associated with a memory device are maintained. A number of program erase cycles associated with the memory device is identified. Responsive to determining that the number of program erase cycles satisfies a criterion, one or more adjusted media scan parameters are generated by adjusting the one or more media scan parameters. A media scan of the memory device is performed according to the one or more adjusted media scan parameters.

A system includes a plurality of storage units each including a network port operably coupled to the network, where one or more storage vaults is associated with the plurality of storage units and each storage vault of the one or more storage vaults represents a software-constructed grouping of storage units of the plurality of storage units, where the software-constructed grouping of storage units stores encoded data slices, where a data segment is encoded using an information dispersal algorithm to produce the encoded data slices, and where a storage unit: receives, via the network port, a request regarding the data segment stored in the software-constructed grouping of storage units, obtains, from a data structure pertaining to the software-constructed grouping of storage units, information regarding the request, determines whether the request is valid based on the information regarding the request, and when the request is valid, the storage unit executes the request.

A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one further processor memory mapped peripheral to control the sharing of the data, wherein the memory mapped peripheral includes a sender part including a data request generator configured to output a data request indicator to the further processor module dependent on a data request register write signal from the processor; and an acknowledgement waiting signal generator configured to output an acknowledgement waiting signal to the processor dependent on a data acknowledgement signal from the further processor module, wherein the data request generator data request indicator is further dependent on the data acknowledgement signal and the acknowledgement waiting signal generator acknowledgement waiting signal is further dependent on the acknowledgement waiting register write signal.

Techniques provide storage space balance for a file system. Along these lines, it is determined whether a first allocation proportion of a first metadata storage space of a first type of metadata from among one or more types of metadata of a file system is greater than a first threshold proportion. If the first allocation proportion is greater than the first threshold proportion, a metadata storage space is reserved for the first type of metadata from a storage space of the file system.

A processing device in a memory sub-system assigns each of a plurality of memory units associated with one or more memory die of a memory device a unique address by which each of the plurality of memory units is identified. The processing device further sends a multi-unit status command to the memory device, the multi-unit status command specifying a subset of the plurality of memory units using corresponding unique addresses and receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.

Fabric modules in a storage system offer differing device IDs from a deterministic sequence to a storage device being added to the storage system. The storage device that is being added accepts a device ID that is higher in the deterministic sequence. The fabric module that offered the device ID same as was accepted by the storage device determines to proceed with initializing the storage device.

The described technology is generally directed towards a streaming data storage system that can switch between a tiered mode of operation in which events are written to Tier-1 storage and later migrated to Tier-2 storage, and a direct mode of operation in which events are written to Tier-2 storage, bypassing the tiered mode. The switching from tiered mode to direct mode, and from direct mode to tiered mode, can be automatic and based on user configuration information. For example, an event size metric (e.g., average event size) can be evaluated against user defined thresholds to determine which mode to use. If the average event size goes below a low threshold value, the tiered mode is switched to and used for appending events to a segment of a data stream. If the average event size goes above a high threshold value, the direct mode is switched to and used.

A method, computer program product, and computing system for receiving a re-initialization operation request for a storage array, the storage array including a plurality of self-encrypting drives. A reversion state may be determined for each self-encrypting drive of the plurality of self-encrypting drives. In response to determining that at least one self-encrypting drive is in an unreverted state, at least one predefined reversion key for reverting the at least one self-encrypting drive from a predefined area of the storage array may be accessed. Each self-encrypting drive of the plurality of self-encrypting drives in the unreverted state may be reverted to a reverted state using the at least one predefined reversion key.

A dual-server based storage system maintains a first cache and a first non-volatile storage (NVS) in a first server, and a second cache and a second NVS in a second server, where data in the first cache is also written in the second NVS and data in the second cache is also written in the first NVS. In response to a failure of the first server, a determination is made as to whether space exists in the second NVS to accommodate the data stored in the second cache. In response to determining that space exists in the second NVS to accommodate the data stored in the second cache, the data is transferred from the second cache to the second NVS.

A storage controller including: a host interface circuit receiving first, second, third and fourth requests corresponding to first, second, third and fourth logical addresses; a memory interface circuit communicating with first nonvolatile memories through a first channel and second nonvolatile memories through a second channel; a first flash translation layer configured to manage the first nonvolatile memories; and a second flash translation layer configured to manage the second nonvolatile memories, the first flash translation layer outputs commands corresponding to the first and fourth requests through the first channel, and the second flash translation layer outputs commands respectively corresponding to the second and third requests through the second channel, and a value of the first logical address is smaller than a value of the second logical address, and a value of the third logical address is smaller than a value of the fourth logical address.