A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.

A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.

A control system includes a data access circuit and a control circuit. The system coordinates an asynchronous FIFO process between a write circuit operating according to a first clock and a read circuit operating according to a second clock. The data access circuit controls the write circuit to write data into a memory buffer and controls the read circuit to read the data from the memory buffer. The control circuit generates a write index according to the first clock and a read index according to the second clock. The control circuit calculates multiple water levels according to the write index and the read index and obtains a median water level. The control circuit controls the access circuit to execute the asynchronous FIFO process at a time point corresponding to the median water level, so that a data exchange is performed via the memory buffer.

A control system includes a data access circuit and a control circuit. The system coordinates an asynchronous FIFO process between a write circuit operating according to a first clock and a read circuit operating according to a second clock. The data access circuit controls the write circuit to write data into a memory buffer and controls the read circuit to read the data from the memory buffer. The control circuit generates a write index according to the first clock and a read index according to the second clock. The control circuit calculates multiple water levels according to the write index and the read index and obtains a median water level. The control circuit controls the access circuit to execute the asynchronous FIFO process at a time point corresponding to the median water level, so that a data exchange is performed via the memory buffer.

A method includes transmitting, by a controller of a storage device, a first bit on a data line. The method further includes responsive to transmitting the first bit on the data line, determining, by the controller, a line level of the data line. The method further includes responsive to determining the line level of the data line, determining, by the controller, whether the line level of the data line corresponds to the first bit and responsive to determining that the line level of the data line does not correspond to the first bit, determining, by the controller, that a collision has occurred on the data line.

A method includes transmitting, by a controller of a storage device, a first bit on a data line. The method further includes responsive to transmitting the first bit on the data line, determining, by the controller, a line level of the data line. The method further includes responsive to determining the line level of the data line, determining, by the controller, whether the line level of the data line corresponds to the first bit and responsive to determining that the line level of the data line does not correspond to the first bit, determining, by the controller, that a collision has occurred on the data line.

An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.

An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.

A control system includes a data access circuit and a control circuit. The system coordinates an asynchronous FIFO process between a write circuit operating according to a first clock and a read circuit operating according to a second clock. The data access circuit controls the write circuit to write data into a memory buffer and controls the read circuit to read the data from the memory buffer. The control circuit generates a write index according to the first clock and a read index according to the second clock. The control circuit calculates multiple water levels according to the write index and the read index and obtains a median water level. The control circuit controls the access circuit to execute the asynchronous FIFO process at a time point corresponding to the median water level, so that a data exchange is performed via the memory buffer.

A control system includes a data access circuit and a control circuit. The system coordinates an asynchronous FIFO process between a write circuit operating according to a first clock and a read circuit operating according to a second clock. The data access circuit controls the write circuit to write data into a memory buffer and controls the read circuit to read the data from the memory buffer. The control circuit generates a write index according to the first clock and a read index according to the second clock. The control circuit calculates multiple water levels according to the write index and the read index and obtains a median water level. The control circuit controls the access circuit to execute the asynchronous FIFO process at a time point corresponding to the median water level, so that a data exchange is performed via the memory buffer.