A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.

A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.

The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.

The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.

A method and an apparatus for generating information based on a FIFO memory, a device and a medium. In the method, a write credit score and a read credit score of a current FIFO memory are determined by a total capacity of the FIFO memory, and a read address, a write address, a read data enable signal value and a write data enable signal value of the current FIFO memory; and the write credit score represents the number of data sets that can be written into the FIFO memory normally; and the read credit score represents the number of data sets that can be read from the FIFO memory normally; and after sending the write credit score and the read credit score to a preceding-stage device, the preceding-stage device read and write data according to the write credit score and the read credit score.

A method and an apparatus for generating information based on a FIFO memory, a device and a medium. In the method, a write credit score and a read credit score of a current FIFO memory are determined by a total capacity of the FIFO memory, and a read address, a write address, a read data enable signal value and a write data enable signal value of the current FIFO memory; and the write credit score represents the number of data sets that can be written into the FIFO memory normally; and the read credit score represents the number of data sets that can be read from the FIFO memory normally; and after sending the write credit score and the read credit score to a preceding-stage device, the preceding-stage device read and write data according to the write credit score and the read credit score.

The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.

A circuit and method for performing a Binary-to-Gray conversion are disclosed. A first binary signal represents a target value and a second binary signal is stored in a register. A set of binary candidate values are determined where the respective Gray equivalent of each binary candidate value has a Hamming distance of one from the Gray equivalent of the second binary value. One of the binary candidate values is selected as a function of the first binary signal and the second binary signal. The selected binary candidate value is provided at input to the register. An encoded signal is generated by determining the Gray encoded equivalent of the selected binary candidate value.

A circuit and method for performing a Binary-to-Gray conversion are disclosed. A first binary signal represents a target value and a second binary signal is stored in a register. A set of binary candidate values are determined where the respective Gray equivalent of each binary candidate value has a Hamming distance of one from the Gray equivalent of the second binary value. One of the binary candidate values is selected as a function of the first binary signal and the second binary signal. The selected binary candidate value is provided at input to the register. An encoded signal is generated by determining the Gray encoded equivalent of the selected binary candidate value.

In an example, a method includes copying a base state of a virtual machine from a source volume to a destination volume, the destination volume having a physical capacity and a virtual capacity, the virtual capacity being larger than the physical capacity, and including a plurality of storage blocks. The method further includes, in response to an instruction to write data to the destination volume, writing the data to at least a first storage block in the plurality of storage blocks and setting a primary flag included in metadata stored on the destination volume from a first state to a second state, where the primary flag is associated with the first storage block. The method further includes subsequently reading a state of the primary flag to determine that data in the first storage block no longer form part of the base state of the virtual machine.