A buffer controller includes a pointer generator, a code converter, a synchronizer, a code restorer, and a comparator. The pointer generator operates according to a first clock signal, and generates a first pointer by encoding a first address of a buffer with a first code. The code converter generates a first transmission pointer by converting the first pointer with a second code or a third code according to an amount of data stored in or read from the first address. The synchronizer synchronizes the first transmission pointer with a second clock signal. The code restorer generates a first comparison pointer by restoring the first transmission pointer, synchronized with the second clock signal, with the first code. The comparator compares the first comparison pointer with a second pointer. The second pointer defines a second address of the buffer with the first code.

A buffer controller includes a pointer generator, a code converter, a synchronizer, a code restorer, and a comparator. The pointer generator operates according to a first clock signal, and generates a first pointer by encoding a first address of a buffer with a first code. The code converter generates a first transmission pointer by converting the first pointer with a second code or a third code according to an amount of data stored in or read from the first address. The synchronizer synchronizes the first transmission pointer with a second clock signal. The code restorer generates a first comparison pointer by restoring the first transmission pointer, synchronized with the second clock signal, with the first code. The comparator compares the first comparison pointer with a second pointer. The second pointer defines a second address of the buffer with the first code.

An electronic device according to some example embodiments includes a clock management circuit configured to control a clock signal and a processor circuit directly connected to the clock management circuit and configured to provide a clock control request for the clock signal to the clock management circuit according to an operation status of the processor circuit.

An electronic device according to some example embodiments includes a clock management circuit configured to control a clock signal and a processor circuit directly connected to the clock management circuit and configured to provide a clock control request for the clock signal to the clock management circuit according to an operation status of the processor circuit.

A sorter receives a list of elements to be sorted. The elements are supplied to a communication bus. A plurality of processing modules are coupled to the communication bus and examine each list element supplied on the bus to see if the list element has a value that is within a range of values processed by the list element. The range of values of the list are subdivided to ranges allocated to the processing modules. When a processing modules determines an element in the bus is within its range, it stores the value and sorts the value in storage dedicated to storing a sorted list of values with the allocated range.

A sorter receives a list of elements to be sorted. The elements are supplied to a communication bus. A plurality of processing modules are coupled to the communication bus and examine each list element supplied on the bus to see if the list element has a value that is within a range of values processed by the list element. The range of values of the list are subdivided to ranges allocated to the processing modules. When a processing modules determines an element in the bus is within its range, it stores the value and sorts the value in storage dedicated to storing a sorted list of values with the allocated range.

In the present invention an alkali vapor cell is proposed comprising a sealed chamber enclosing an alkali atomic gas therein and having at least one optically transparent window. The chamber and the transparent window define an optical beam path through which a light beam can pass and which interacts with the alkali atomic gas in the chamber. The alkali vapor cell comprises at least one localized condensation area of alkali atoms at a predetermined location in the sealed chamber and the predetermined location is located inside or outside the optical beam path. The localized condensation area has higher alkali metal wettability than any other surface portion of the alkali vapor cell outside said localized condensation area.

A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.

A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.

A circuit and method for performing a Binary-to-Gray conversion are disclosed. A first binary signal represents a target value and a second binary signal is stored in a register. A set of binary candidate values are determined where the respective Gray equivalent of each binary candidate value has a Hamming distance of one from the Gray equivalent of the second binary value. One of the binary candidate values is selected as a function of the first binary signal and the second binary signal. The selected binary candidate value is provided at input to the register. An encoded signal is generated by determining the Gray encoded equivalent of the selected binary candidate value.