Low precision computers can be efficient at finding possible answers to search problems. However, sometimes the task demands finding better answers than a single low precision search. A computer system augments low precision computing with a small amount of high precision computing, to improve search quality with little additional computing.

Low precision computers can be efficient at finding possible answers to search problems. However, sometimes the task demands finding better answers than a single low precision search. A computer system augments low precision computing with a small amount of high precision computing, to improve search quality with little additional computing.

A system includes a memory and a node. The memory stores first and second log string correlithm objects. The node aligns the first and second log string correlithm objects such that a sub-string correlithm object from the first log string correlithm object associated with the logarithmic value of ten aligns with a sub-string correlithm object from the second log string correlithm object representing the logarithmic value of one. The node receives a first real-world numerical value and identifies a first sub-string correlithm object from the first log string correlithm object that corresponds to the first real-world numerical value. The node determines which sub-string correlithm object from the second log string correlithm object aligns in n-dimensional space with the first sub-string correlithm object from the first log string correlithm object, and outputs the determined sub-string correlithm object.

Low precision computers can be efficient at finding possible answers to search problems. However, sometimes the task demands finding better answers than a single low precision search. A computer system augments low precision computing with a small amount of high precision computing, to improve search quality with little additional computing.

Low precision computers can be efficient at finding possible answers to search problems. However, sometimes the task demands finding better answers than a single low precision search. A computer system augments low precision computing with a small amount of high precision computing, to improve search quality with little additional computing.

Low precision computers can be efficient at finding possible answers to search problems. However, sometimes the task demands finding better answers than a single low precision search. A computer system augments low precision computing with a small amount of high precision computing, to improve search quality with little additional computing.

A processing unit and a method for multiplying at least two multiplicands. The multiplicands are present in an exponential notation, that is, each multiplicand is assigned an exponent and a base. The processing unit is configured to carry out a multiplication of the multiplicands and includes at least one bitshift unit, the bitshift unit shifting a binary number a specified number of places, in particular, to the left; an arithmetic unit, which carries out an addition of two input variables and a subtraction of two input variables; and a storage device. A computer program, which is configured to execute the method, and a machine-readable storage element, in which the computer program is stored, are also described.

The neural electronic circuit includes: a storage unit (MC) that stores a logarithmic weighting coefficient, in which a value obtained by logarithmizing a weighting coefficient corresponding to input data that is input is expressed in multiple bits, and outputs the logarithmic weighting coefficient bit by bit; a first electronic circuit unit (Pe) that outputs a multiplication result of the input data and the weighting coefficient; and a second electronic circuit unit (Act) that realizes addition and application functions for adding up the multiplication results, applying an activation function to the addition result, and outputting output data. Logarithmic input data expressed in multiple bits is received bit by bit, a logarithmic addition is calculated by adding up the logarithmic input data and the logarithmic weighting coefficient output from the storage unit, the multiplication result is calculated by linearizing the logarithmic addition result, and the output data that is logarithmized is output.

A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).

An integrated circuit including a plurality of logarithmic addition-accumulator circuits, connected in series, to, in operation, perform logarithmic addition and accumulate operations, wherein each logarithmic addition-accumulator circuit includes: (i) a logarithmic addition circuit to add a first input data and a filter weight data, each having the logarithmic data format, and to generate and output first sum data having a logarithmic data format, and (ii) an accumulator, coupled to the logarithmic addition circuit of the associated logarithmic addition-accumulator circuit, to add a second input data and the first sum data output by the associated logarithmic addition circuit to generate first accumulation data. The integrated circuit may further include first data format conversion circuitry, coupled to the output of each logarithmic addition circuit, to convert the data format of the first sum data to a floating point data format wherein the accumulator may be a floating point type.