Aspects for converting floating-point numbers in a processor are described herein. As an example, the aspects may include receiving, by a floating-point number converter, an exponent bit length, a base value, and one or more first floating-point numbers of a first bit length. Further, the aspects may include calculating, by the floating-point number converter, one or more second floating-point numbers of a second bit length based on the exponent bit length and the base value, the one or more second floating-point numbers respectively corresponding to the one or more first floating-point numbers.

An apparatus for recursive processing includes: a memory and a processor configured to in a first step of a plurality of steps in which a specific process is executed, execute a determination process of whether a size of first data to be processed in the first step coincides with a first upper size limit defined based on a state of a second step of the plurality of steps, store a result of the determination process in the memory, and in a third step of the plurality of steps, identify the size of the first data with reference to the result stored in the memory, and execute the specific process of the third step based on the identified size of the first data.

Implementations of the disclosure provide logarithm and anti-logarithm operations on a hardware processor based on linear piecewise approximation. An example processor includes a piece wise linear log approximation circuit that receives an input of a floating-point number comprising a sign, an exponent and a mantissa. The piece wise linear log approximation circuit approximates a fractional portion of a fixed point number using a linear approximation of the mantissa of the floating-point number. The piece wise linear log approximation circuit also derives an integer from the exponent.

An arithmetic processing device includes: a first memory configured to store values of a first coefficient of a logarithmic function, where the logarithmic function is decomposed into a series operation term and the coefficient term, depending on respective values of a first bit group included in operand data of a first instruction to calculate the value of the first coefficient; a second memory configured to store values of a second coefficient included in the series operation term depending on the respective values of the first bit group included in operand data of a second instruction to calculate the value of the second coefficient; and a selector configured to select the value of the first coefficient read from the first memory based on the execution of the first instruction and select the value of the second coefficient read from the second memory based on the execution of the second instruction.

Neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. Compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. However, performing addition on logarithmic format values is more complex. Conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. Instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum. The sum may then be converted back into the logarithmic format.

Neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. Compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. However, performing addition on logarithmic format values is more complex. Conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. Instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components using an asynchronous accumulator to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum. The sum may then be converted back into the logarithmic format.

A decoding apparatus having a non-transient memory in which is stored an electromagnetic signal representative of data which were encrypted relying on the difficulty of computing discrete logarithms. The decoding apparatus has a computer in communication with the memory that decodes the encrypted data in the memory by computing the data's discrete logarithm. The decoding apparatus has a display on which the decoded encrypted data are displayed by the computer. A method for decoding.

In a novel computation device, a plurality of partial product generators is communicatively coupled to a binary number multiplier. The binary number is partitioned in the computation device into non-overlapping subsets of binary bits and each subset is coupled to one of the plurality of partial product generators. Each partial product generator, upon receiving a subset of binary bits representing a number, generates a multiplication product of the number and a predetermined constant. The multiplication products from all partial product generators are summed to generate the final product between the predetermined constant and the binary number. The partial product generators are constructed by logic gates and wires connected the logic gates including a AND gate. The partial product generators are free of memory elements.

Low precision computers can be efficient at finding possible answers to search problems. However, sometimes the task demands finding better answers than a single low precision search. A computer system augments low precision computing with a small amount of high precision computing, to improve search quality with little additional computing.

In order to stabilize numerical computations, an information processing apparatus (1) includes an acquiring means (11) for acquiring a data set and an estimating means (12) for estimating parameters of a Fisher-Bingham distribution which corresponds to the data set, and the estimating means (12) is configured to carry out a parameter estimating process, the parameter estimating process including: calculating a logarithm of a normalizing constant C of the Fisher-Bingham distribution and a logarithm of a derivative of the normalizing constant C; calculating the linear sum of the logarithm of the normalizing constant C and the logarithm of the derivative of the normalizing constant C; and calculating an exponential function the exponent of which is the linear sum.