Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.

A processor is used for performing a floating-point multiply-add operation of a form A*B+C on at least one multiply-add unit, with three input floating-point operands A, B, C, wherein at least one of the operands A, B, C is substituted by at least one value of a predefined operand value set.

A processor is used for performing a floating-point multiply-add operation of a form A*B+C on at least one multiply-add unit, with three input floating-point operands A, B, C, wherein at least one of the operands A, B, C is substituted by at least one value of a predefined operand value set.

A modular operation circuit includes a controller, a modular multiplier and a modular adder. The controller divides a first number into K segments. The modular multiplier performs modular multiplication operations and the modular adder performs modular addition operations to the K segments in (K−1) iterations for deriving a remainder of a division of the first number by a second number.

A modular operation circuit includes a controller, a modular multiplier and a modular adder. The controller divides a first number into K segments. The modular multiplier performs modular multiplication operations and the modular adder performs modular addition operations to the K segments in (K−1) iterations for deriving a remainder of a division of the first number by a second number.

An integrated circuit includes a hardware inexact floating-point logarithmic number system (FPLNS) multiplier. The integrated circuit access registers containing a first floating-point binary value and its first logarithmic binary value and a second floating-point binary value and its second logarithmic binary value, each being in an FPLNS data format. The FPLNS multiplier configured to multiply the first and second floating-point binary values by adding the first logarithmic binary value to the second logarithmic binary value to form a first logarithmic sum, shifting a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value, subtracting a correction factor from the first shifted bias value to form a first corrected bias value, and subtracting the first corrected bias value from the first logarithmic sum to form a first result.

An integrated circuit includes a hardware inexact floating-point logarithmic number system (FPLNS) multiplier. The integrated circuit access registers containing a first floating-point binary value and its first logarithmic binary value and a second floating-point binary value and its second logarithmic binary value, each being in an FPLNS data format. The FPLNS multiplier configured to multiply the first and second floating-point binary values by adding the first logarithmic binary value to the second logarithmic binary value to form a first logarithmic sum, shifting a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value, subtracting a correction factor from the first shifted bias value to form a first corrected bias value, and subtracting the first corrected bias value from the first logarithmic sum to form a first result.

This application discloses a floating-point number multiplication computation method, an apparatus, and an arithmetic logic unit. The method includes: obtaining a plurality of to-be-computed first-precision floating-point numbers; decomposing each to-be-computed first-precision floating-point number to obtain at least two second-precision floating-point numbers, a second precision of the second-precision floating-point number is lower than a first precision of the first-precision floating-point number; determining various combinations including two second-precision floating-point numbers obtained by decomposing different first-precision floating-point numbers; inputting the second-precision floating-point numbers in each combination into a second-precision multiplier to obtain an intermediate computation result corresponding to each combination; and determining a computation result for the plurality of to-be-computed first-precision floating-point numbers based on the intermediate computation result corresponding to each combination.

This application discloses a floating-point number multiplication computation method, an apparatus, and an arithmetic logic unit. The method includes: obtaining a plurality of to-be-computed first-precision floating-point numbers; decomposing each to-be-computed first-precision floating-point number to obtain at least two second-precision floating-point numbers, a second precision of the second-precision floating-point number is lower than a first precision of the first-precision floating-point number; determining various combinations including two second-precision floating-point numbers obtained by decomposing different first-precision floating-point numbers; inputting the second-precision floating-point numbers in each combination into a second-precision multiplier to obtain an intermediate computation result corresponding to each combination; and determining a computation result for the plurality of to-be-computed first-precision floating-point numbers based on the intermediate computation result corresponding to each combination.

A digital signal processor (DSP), which may be implemented as a DSP block in a field programmable gate array (FPGA), includes a fracturable multiplier, a fracturable adder and a fracturable variable shifter. Further included is at least one sign-extension block, to provide for normal mode, dual-fracturing mode and quad-fracturing mode.