A digital signal processor (DSP), which may be implemented as a DSP block in a field programmable gate array (FPGA), includes a fracturable multiplier, a fracturable adder and a fracturable variable shifter. Further included is at least one sign-extension block, to provide for normal mode, dual-fracturing mode and quad-fracturing mode.

A multi-input multi-output adder and an operating method thereof are proposed. The multi-input multi-output adder includes an adder circuitry configured to perform an operation. The operation includes the following. A first source operand and a second source operand are added to generate a first summed operand. Direct truncation is performed on at least one last bit of the first summed operand to generate a first truncated-summed operand. Right shift is performed on the first truncated-summed operand to generate a first shifted-summed operand. A bit number of the right shift of the first truncated-summed operand is equal to a bit number of the direct truncation of the first summed operand.

Disclosed herein are a floating-point computation apparatus and method using Computing-in-Memory (CIM). The floating-point computation apparatus performs a multiply-and-accumulation operation on pieces of input neuron data represented in a floating-point format, and includes a data preprocessing unit configured to separate and extract an exponent and a mantissa from each of the pieces of input neuron data, an exponent processing unit configured to perform CIM on input neuron exponents, which are exponents separated and extracted from the input neuron data, and a mantissa processing unit configured to perform a high-speed computation on input neuron mantissas, separated and extracted from the input neuron data, wherein the exponent processing unit determines a mantissa shift size for a mantissa computation and transfers the mantissa shift size to the mantissa processing unit, and the mantissa processing unit normalizes a result of the mantissa computation and transfers a normalization value to the exponent processing unit.

Disclosed herein are a floating-point computation apparatus and method using Computing-in-Memory (CIM). The floating-point computation apparatus performs a multiply-and-accumulation operation on pieces of input neuron data represented in a floating-point format, and includes a data preprocessing unit configured to separate and extract an exponent and a mantissa from each of the pieces of input neuron data, an exponent processing unit configured to perform CIM on input neuron exponents, which are exponents separated and extracted from the input neuron data, and a mantissa processing unit configured to perform a high-speed computation on input neuron mantissas, separated and extracted from the input neuron data, wherein the exponent processing unit determines a mantissa shift size for a mantissa computation and transfers the mantissa shift size to the mantissa processing unit, and the mantissa processing unit normalizes a result of the mantissa computation and transfers a normalization value to the exponent processing unit.

An arithmetic processing apparatus includes a processor. The processor is configured to execute a parallel calculation on a plurality of pieces of floating-point data; determine whether or not information loss is to occur in the parallel calculation; and output a result of the parallel calculation when it is determined that the information loss is not to occur, and execute a sequential calculation on the plurality of pieces of floating-point data to output the result of the sequential calculation when it is determined that the information loss is to occur.

An arithmetic processing apparatus includes a processor. The processor is configured to execute a parallel calculation on a plurality of pieces of floating-point data; determine whether or not information loss is to occur in the parallel calculation; and output a result of the parallel calculation when it is determined that the information loss is not to occur, and execute a sequential calculation on the plurality of pieces of floating-point data to output the result of the sequential calculation when it is determined that the information loss is to occur.

Provided are embodiments for a circuit comprising for performing hardware acceleration for elliptic curve cryptography (ECC). The circuit includes a code array comprising instructions for performing complex modular arithmetic; and a data array storing values corresponding to one or more complex numbers. The modular arithmetic unit includes a first multiplier and a first accumulation unit, a second multiplier and a second accumulation unit, and a third multiplier and a third accumulation unit, wherein the first, second, and third multiplier and accumulation units are cascaded and configured to perform hardware computation of complex modular operations. Also provided are embodiments of a computer program product and a method for performing the hardware acceleration of super-singular isogeny key encryption (SIKE) operations.

Provided are embodiments for a circuit comprising for performing hardware acceleration for elliptic curve cryptography (ECC). The circuit includes a code array comprising instructions for performing complex modular arithmetic; and a data array storing values corresponding to one or more complex numbers. The modular arithmetic unit includes a first multiplier and a first accumulation unit, a second multiplier and a second accumulation unit, and a third multiplier and a third accumulation unit, wherein the first, second, and third multiplier and accumulation units are cascaded and configured to perform hardware computation of complex modular operations. Also provided are embodiments of a computer program product and a method for performing the hardware acceleration of super-singular isogeny key encryption (SIKE) operations.

Apparatus and a corresponding method are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.

Apparatus and a corresponding method are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.