A modular operation circuit includes a controller, a modular multiplier and a modular adder. The controller divides a first number into K segments. The modular multiplier performs modular multiplication operations and the modular adder performs modular addition operations to the K segments in (K−1) iterations for deriving a remainder of a division of the first number by a second number.

Provided are a method and apparatus for a hardware-based accelerated arithmetic operation on homomorphically encrypted messages. The method of performing hardware-based modular multiplication on homomorphically encrypted messages according to the present invention includes receiving a plurality of homomorphically encrypted messages expressed in a polynomial form and a modulus for modular multiplication, decomposing the modulus into a product of a plurality of disjoint factors through CRT operation, and extracting a divided ciphertext from a plurality of homomorphically encrypted messages based on each of the disjoint factors, performing NTT transformation on each coefficient of the divided ciphertext, performing a pointwise multiplication operation between result values of the NTT transformation, performing INTT transformation on a result value of the pointwise multiplication operation to obtain the divided ciphertext, and merging the divided ciphertext obtained in the performing of the INTT transformation through ICRT operation to generate an output ciphertext.

A product-sum calculation device multiplies first and second floating-point numbers and sequentially adds multiplication results. The device adds a first exponent and a second exponent of the respective floating-point numbers for generating a third exponent, multiplies a first mantissa and a second mantissa of the respective floating-point numbers for generating a third mantissa, sets lower n bits of the third exponent to zero and generates a fourth exponent, shifts the third mantissa to the left by the number of bits indicated by the lower n bits and generated a fourth mantissa, generates an error detection code for each 2.sup.n bits of the fourth mantissa, performs digit alignment of the fourth mantissa and a fifth mantissa and outputs an exponent as a new fifth exponent, and adds the fourth mantissa and the fifth mantissa and outputs an addition result as a new fifth mantissa.

An integrated circuit includes a hardware inexact floating-point logarithmic number system (FPLNS) multiplier. The integrated circuit access registers containing a first floating-point binary value and its first logarithmic binary value and a second floating-point binary value and its second logarithmic binary value, each being in an FPLNS data format. The FPLNS multiplier configured to multiply the first and second floating-point binary values by adding the first logarithmic binary value to the second logarithmic binary value to form a first logarithmic sum, shifting a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value, subtracting a correction factor from the first shifted bias value to form a first corrected bias value, and subtracting the first corrected bias value from the first logarithmic sum to form a first result.

This application discloses a floating-point number multiplication computation method, an apparatus, and an arithmetic logic unit. The method includes: obtaining a plurality of to-be-computed first-precision floating-point numbers; decomposing each to-be-computed first-precision floating-point number to obtain at least two second-precision floating-point numbers, a second precision of the second-precision floating-point number is lower than a first precision of the first-precision floating-point number; determining various combinations including two second-precision floating-point numbers obtained by decomposing different first-precision floating-point numbers; inputting the second-precision floating-point numbers in each combination into a second-precision multiplier to obtain an intermediate computation result corresponding to each combination; and determining a computation result for the plurality of to-be-computed first-precision floating-point numbers based on the intermediate computation result corresponding to each combination.

This application discloses a floating-point number multiplication computation method, an apparatus, and an arithmetic logic unit. The method includes: obtaining a plurality of to-be-computed first-precision floating-point numbers; decomposing each to-be-computed first-precision floating-point number to obtain at least two second-precision floating-point numbers, a second precision of the second-precision floating-point number is lower than a first precision of the first-precision floating-point number; determining various combinations including two second-precision floating-point numbers obtained by decomposing different first-precision floating-point numbers; inputting the second-precision floating-point numbers in each combination into a second-precision multiplier to obtain an intermediate computation result corresponding to each combination; and determining a computation result for the plurality of to-be-computed first-precision floating-point numbers based on the intermediate computation result corresponding to each combination.

A digital signal processor (DSP), which may be implemented as a DSP block in a field programmable gate array (FPGA), includes a fracturable multiplier, a fracturable adder and a fracturable variable shifter. Further included is at least one sign-extension block, to provide for normal mode, dual-fracturing mode and quad-fracturing mode.

A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

Disclosed in the present disclosure is an FPGA implementation device and method for an FBLMS algorithm based on block floating point. The method includes: blocking, caching, and reassembling a reference signal, by an input caching and converting module, converting into a block floating point system and performing FFT; filtering, by a filtering module, in a frequency domain and performing dynamic truncation; caching, by an error calculating and output caching module, a target signal on a block basis, converting into a block floating point system, subtracting an output result output from the filtering module from the converted target signal to obtain an error signal, converting the error signal into a fixed point system to obtain a final cancellation result; obtaining, by a weight adjustment amount calculating module and a weight updating and storing module, an adjustment amount of a frequency domain block weight and updating the frequency domain block weight.

A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a:b]mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M−1 modulo units of the logarithmic tree provide x[0:m]mod d for all m∈{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of ┌log .sub.2M┐; and more than M−2.sup.u of the subset of modulo units are arranged at the maximal delay of ┌log .sub.2M┐, where 2.sup.u is the power of 2 immediately smaller than M.