A system, structure and method using radix-1000 (instead of radix-10) are implemented to represent and operate on decimal floating-point numbers. Instead of using a 10-bit declet to encode a DPD, the system, structure and method herein use a declet to encode a BCK (Binary Coded 1000 values), where the letter K is the abbreviation of the number 1000. A skewed representation of the fraction field is then used to avoid the loss of decimal digits in arithmetic operations when shifting and rounding the fraction are required.

An apparatus and method are provided for subtracting a first significand value of a first floating-point operand and a second significand value of a second floating-point operand. Significand shift control circuitry asserts a shift signal when a difference is detected between at least one corresponding low order bit in the exponent values of the two floating-point operands. First processing circuitry is arranged to produce a first difference value by performing a first subtraction operation to subtract the second significand value from the first significand value when the shift signal is unasserted, and to subtract a right-shifted version of the second significand value from the first significand value when the shift signal is asserted. Second processing circuitry is arranged to produce a second difference value by performing a second subtraction operation to subtract the first significand value from the second significand value when the shift signal is unasserted, and to subtract a right-shifted version of the first significand value from the second significand value when the shift signal is asserted. First shift estimation circuitry is arranged to determine, from the significand values subjected to the first subtraction operation, a first estimated left shift amount, and similarly second shift estimation circuitry is arranged to determine, from the significand values subjected to the second subtraction operation, a second estimated left shift amount. Shifted difference value generation circuitry then produces, as a shifted difference value, the first difference value left shifted by the first estimated left shift amount when the first difference value is non-negative, and the second difference value left shifted by the second estimated left shift amount when the second difference value is non-negative. Such an approach can significantly reduce the time taken to generate a normalized difference value.

An apparatus and method are provided for subtracting a first significand value of a first floating-point operand and a second significand value of a second floating-point operand. Significand shift control circuitry asserts a shift signal when a difference is detected between at least one corresponding low order bit in the exponent values of the two floating-point operands. First processing circuitry is arranged to produce a first difference value by performing a first subtraction operation to subtract the second significand value from the first significand value when the shift signal is unasserted, and to subtract a right-shifted version of the second significand value from the first significand value when the shift signal is asserted. Second processing circuitry is arranged to produce a second difference value by performing a second subtraction operation to subtract the first significand value from the second significand value when the shift signal is unasserted, and to subtract a right-shifted version of the first significand value from the second significand value when the shift signal is asserted. First shift estimation circuitry is arranged to determine, from the significand values subjected to the first subtraction operation, a first estimated left shift amount, and similarly second shift estimation circuitry is arranged to determine, from the significand values subjected to the second subtraction operation, a second estimated left shift amount. Shifted difference value generation circuitry then produces, as a shifted difference value, the first difference value left shifted by the first estimated left shift amount when the first difference value is non-negative, and the second difference value left shifted by the second estimated left shift amount when the second difference value is non-negative. Such an approach can significantly reduce the time taken to generate a normalised difference value.

An integrated circuit may include a floating-point adder that supports variable precisions. The floating-point adder may receive first and second inputs to be added, where the first and second inputs each have a mantissa and an exponent. The mantissa and exponent values may be split into a near path and a far path using a dual path floating-point adder architecture depending on the difference of the exponents and on whether an addition or subtraction is being performed. The mantissa values may be left justified, while the sticky bits are right justified. The hardware for the largest mantissa can be used to support the calculations for the smaller mantissas using no additional arithmetic structures, with only some multiplexing and decoding logic.

An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (C.sub.in), and two consecutive bits for carry-out-bar (C.sub.out), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.

An integrated circuit may include a floating-point adder that supports variable precisions. The floating-point adder may receive first and second inputs to be added, where the first and second inputs each have a mantissa and an exponent. The mantissa and exponent values may be split into a near path and a far path using a dual path floating-point adder architecture depending on the difference of the exponents and on whether an addition or subtraction is being performed. The mantissa values may be left justified, while the sticky bits are right justified. The hardware for the largest mantissa can be used to support the calculations for the smaller mantissas using no additional arithmetic structures, with only some multiplexing and decoding logic.

Embodiments of the present disclosure relate to storing parameters representing nonlinear functions in programmable memory circuits of a neural processor circuit and reusing the stored parameters across multiple tasks. The parameters are initially included in a task descriptor defining the configuration of the neural processor circuit for a task and are programmed into programmable memory circuits. Parameters for other nonlinear functions are stored in non-programmable memory circuits. In subsequent tasks, the stored parameters are reused to generate activation values for applying to processed output from multiply-accumulate (MAC) circuit by indicating, in task descriptors for the subsequent tasks, programmable or nonprogrammable memory circuits from which the parameters are to be retrieved. By replacing the parameters of the nonlinear functions with the indication of the memory circuits in the subsequent tasks, the amount of data to be included in the task descriptors of the subsequent tasks is reduced.