A method includes receiving an input data at a FP arithmetic operating unit configured to perform a FP arithmetic operation on the input data. The method further includes determining whether the received input data generates a FP hardware exception responsive to the FP arithmetic operation on the input data, wherein the determining occurs prior to performing the FP arithmetic operation. The method also includes converting a value of the received input data to a modified value responsive to the determining that the received input data generates the FP hardware exception, wherein the converting eliminates generation of the FP hardware exception responsive to the FP arithmetic operation on the input data.

A method includes receiving an input data at a FP arithmetic operating unit configured to perform a FP arithmetic operation on the input data. The method further includes determining whether the received input data generates a FP hardware exception responsive to the FP arithmetic operation on the input data, wherein the determining occurs prior to performing the FP arithmetic operation. The method also includes converting a value of the received input data to a modified value responsive to the determining that the received input data generates the FP hardware exception, wherein the converting eliminates generation of the FP hardware exception responsive to the FP arithmetic operation on the input data.

The invention introduces a method for calculating floating-point operands, which contains at least the following steps: receiving an FP (floating-point) operand in a first format from a source register, wherein the first format is one of a group of first formats of different kinds; converting the FP operand in the first format into an FP operand in a second format; generating a calculation result in the second format by calculating the FP operand in the second format; converting the calculation result in the second format into a calculation result in the first format; and writing-back the calculation result of the first format.

Generating data structures for computer memory. Provisional data structures are generated that respectively have (i) a significand with an initial value of zero and (ii) an exponent that is included in a range of exponents. A test data structure from a provisional data structure by modifying a significand of the first provisional data structure using a significand of a floating-point number such that the significand of the first provisional data structure has a non-zero value. Modifying at least one provisional data structure based on a content of the test data structure. Generating a new data structure that represents the contents of a plurality of provisional-data structures. The plurality of provisional data structures includes at least one provisional data structure that was modified to include the significands of at least two floating-point numbers. The new data structure represents a value that is expressible by a limited number of memory bits.

An apparatus and method are provided for processing floating point values using an intermediate representation which has significand, exponent and shadow sections. A less significant portion of the exponent of the floating point value defines a range of positions within the significand section where the representation of the significand is to be held. The exponent section holds a representation of a more significant portion of the exponent indicating a selected window of multiple contiguous windows spanning a value range of a format of the floating point value. A first portion of the significand section corresponds to the selected window and a second portion corresponds to an overlap into a further window which is adjacent to and lower in the value range. The shadow section holds values for populating the second portion of the significand section when the representation of the significand of the floating point value is moved to a higher window which is adjacent to and higher in the value range than the selected window. The shadow section allows the selected window to be shifted, such that the summation of multiple values produces the same result independent of the order in which the values are summed.

Introduced here is a technique to detect and/or correct errors in computation. The ability to correct errors in computation can increase the speed of the processor, reduce the power consumption of the processor, and reduce the distance between the transistors within the processor because the errors thus generated can be detected and corrected. In one embodiment, an error correcting module, running either in software or in hardware, can detect an error in matrix multiplication, by calculating an expected sum of all elements in the resulting matrix, and an actual sum of all elements in the resulting matrix. When there is a difference between the expected sum and the resulting sum, the error correcting module detects an error. In another embodiment, in addition to detecting the error, the error correcting module can determine the location and the magnitude of the error, thus correcting the erroneous computation.

Systems and methods evaluate simulation models and measure floating point arithmetic errors in terms of Unit in Last Place (ULP). The simulation model may include model elements that perform numerical computations using Native Floating Point (NFP) arithmetic. The model elements may be arranged to implement a procedure. A data store may include local ULP errors predetermined for the model elements. The systems and methods may retrieve the local ULP errors for the model elements included in the model, and may apply a rules-based analysis to compute an overall ULP error of the simulation model. The systems and methods may present the overall ULP computed for the model. The systems and methods may also present intermediate ULP errors determined for portions of the simulation model. Changes may be made to the model to reduce the overall ULP error.

Systems and methods are directed to accelerating operations associated with a microprocessor. Example embodiments improve the operations of the microprocessor by providing devices (e.g., integrated circuits, independent accelerators) configured to use reciprocal or reciprocal square root instructions. Such devices can be further configured to follow the reciprocal or reciprocal square root instructions with multiplication or other instructions to finish division, square root, or other complex operations.

Generating data structures for computer memory. Provisional data structures are generated that respectively have (i) a significand with an initial value of zero and (ii) an exponent that is included in a range of exponents. A test data structure from a provisional data structure by modifying a significand of the first provisional data structure using a significand of a floating-point number such that the significand of the first provisional data structure has a non-zero value. Modifying at least one provisional data structure based on a content of the test data structure. Generating a new data structure that represents the contents of a plurality of provisional-data structures. The plurality of provisional data structures includes at least one provisional data structure that was modified to include the significands of at least two floating-point numbers. The new data structure represents a value that is expressible by a limited number of memory bits.

A method for enhancing an accuracy of a sum of a plurality of floating-point numbers. The method receives a floating-point number and generates a plurality of provisional numbers with a value of zero. The method further generates a surjective map from the values of an exponent and a sign of a mantissa to the provisional numbers in the plurality of provisional numbers. The method further maps a value of the exponent and the sign of the mantissa to a first provisional number with the surjective map. The method further generates a test number from the first provisional number and if the test number exceeds a limit, modifies a second provisional number by using at least part of the test number. The method further equates the first provisional number to the test number if the test number does not exceed the limit. The method further sums the plurality of provisional numbers.