An apparatus to facilitate a computer number format conversion is disclosed. The apparatus comprises a control unit to receive to receive data format information indicating a first precision data format that input data is to be received and converter hardware to receive the input data and convert the first precision data format to a second precision data format based on the data format information.

An arithmetic processing device includes a memory and a processor coupled to memory. The processor configured to acquire a first operation result of a first operation executing by using a candidate decimal point position, determine a specific decimal point position determined based on statistical information of the first operation result, and acquires, as a final operation result, either the first operation result or a second operation result of a second operation executing by using the specific decimal point position, based on the candidate decimal point position and the specific decimal point position.

An arithmetic processing apparatus includes: a memory that stores, when a training of a given machine learning model is repeatedly performed in a plurality of iterations, an error of a decimal point position of each of a plurality of fixed-point number data obtained one in each of the plurality of iterations, the error being obtained baaed on statistical information related to a distribution of leftmost set bit positions for positive number and leftmost unset bit positions for negative number or a distribution of rightmost set bit positions of the plurality of fixed-point number data; and a processor coupled to the memory, the processor being configured to: determine, based on a tendency of the error in each of the plurality of iterations, an offset amount for correcting a decimal point position of fixed-point number data used in the training.

A method for approximating an activation function, the method including: receiving an input value of the activation function; determining that the input value is within a range, the range includes a set of non-uniform intervals; determining a selected interval from among the set of non-uniform intervals including the input value; retrieving, by a hardware accelerator, from a look-up table (LUT) associated with a type of the activation function, values of one or more quadratic interpolation parameters associated with the selected interval; performing a quadratic interpolation on the input value to approximate the input value using the values of the one or more quadratic interpolation parameters; and determining a first approximated output of the activation function based on a result of the quadratic interpolation performed on the input value.

An arithmetic processing apparatus includes: a first determiner that determines, when a given learning model is repeatedly learned, an offset amount for correcting a decimal point position of fixed-point number data used in the learning in accordance with a degree of progress of the learning; and a second determiner that determines, based on the offset amount, the decimal point position of the fixed-point number data to be used in the learning. This configuration avoids lowering of the accuracy of a learning result of a learning model.

Examples of techniques for hexadecimal exponent alignment for a binary floating point unit (BFU) of a computer processor are described herein. An aspect includes receiving, by the BFU, a first operand comprising a first fraction and a first exponent, and a second operand comprising a second fraction and a second exponent. Another aspect includes, based on the first operand and the second operand being in a first floating point format, multiplying each of the first exponent and the second exponent by a factor corresponding to a number of bits in a digit in the first floating point format.

The invention relates to improved convolutions of digital signals. When a first digital signal is convoluted with a second digital signal to obtain an output digital signal, to be converted afterwards using a limited number of bits. In order to prevent a loss of information, and therefore a degradation of the output digital signal upon the future conversion, at least one of the first and the second digital signal is formed of suitable values that store the information from the first digital signal within the most significant bits of the output digital signal.

The invention relates to the representation of digital signals. In order to improve the perception by a user of the quality of a digital signal, a first sample of first digital signal is approximated to a second sample of a second digital signal having a second number of significant bits lower than the first number of significant bits of the first sample. The second number of significant bits also depends upon the value of the first sample.

A microprocessor provides at least two storage areas and uses a datapath for Booth multiplication. According to a first and second field of a microinstruction, the datapath gets multiplicand number supply data from the first storage area and multiplier number supply data from the second storage area. The datapath operates according to a word length indicated in a third field of the microinstruction. The datapath gets multi-bit acquisitions for Booth multiplication from the multiplier number supply data. The datapath divides the multiplicand number supply data into multiplicand numbers according to the word length, and performs Booth multiplication on the multiplicand numbers based on the multi-bit acquisitions to get partial products. According to the word length, the datapath selects a part of the partial products to be shifted and added for generation of a plurality of products.

A microprocessor with dynamically adjustable bit width is provided, which has a bit width register, a datapath, a statistical register, and a bit width adjuster. The bit width register stores at least one bit width. The datapath operates according to the bit width stored in the bit width register to acquire input operands from received data and process input operands. The statistical register collects calculation results of the datapath. The bit width adjuster adjusts the bit width stored in the bit width register based on the calculation results collected in the statistical register.